Lines Matching refs:base
228 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
238 .enable_reg = (base), \
243 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
254 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
256 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
259 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
264 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
274 .vsel_reg = (base), \
276 .enable_reg = (base), \
281 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
292 .vsel_reg = (base), \
294 .enable_reg = (base), \
297 .stby_reg = (base), \
301 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
311 .vsel_reg = (base), \
313 .enable_reg = (base), \
318 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
328 .vsel_reg = (base), \
330 .enable_reg = (base), \
333 .stby_reg = (base), \
338 #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
348 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
350 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
355 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
360 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
370 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
373 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \