Lines Matching refs:base
220 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
230 .enable_reg = (base), \
235 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
246 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
248 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
251 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
256 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
266 .vsel_reg = (base), \
268 .enable_reg = (base), \
273 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
284 .vsel_reg = (base), \
286 .enable_reg = (base), \
289 .stby_reg = (base), \
293 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
303 .vsel_reg = (base), \
305 .enable_reg = (base), \
310 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
320 .vsel_reg = (base), \
322 .enable_reg = (base), \
325 .stby_reg = (base), \
330 #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
340 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
342 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
347 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
352 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
362 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
365 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \