1 // SPDX-License-Identifier: GPL-2.0
2 /* Ethernet device driver for Cortina Systems Gemini SoC
3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
4 * Net Engine and Gigabit Ethernet MAC (GMAC)
5 * This hardware contains a TCP Offload Engine (TOE) but currently the
6 * driver does not make use of it.
7 *
8 * Authors:
9 * Linus Walleij <linus.walleij@linaro.org>
10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
12 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
14 * Gary Chen & Ch Hsu Storlink Semiconductor
15 */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/cache.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26 #include <linux/clk.h>
27 #include <linux/of.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/of_platform.h>
31 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/skbuff.h>
34 #include <linux/phy.h>
35 #include <linux/crc32.h>
36 #include <linux/ethtool.h>
37 #include <linux/tcp.h>
38 #include <linux/u64_stats_sync.h>
39
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/ipv6.h>
43
44 #include "gemini.h"
45
46 #define DRV_NAME "gmac-gemini"
47
48 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
49 static int debug = -1;
50 module_param(debug, int, 0);
51 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
52
53 #define HSIZE_8 0x00
54 #define HSIZE_16 0x01
55 #define HSIZE_32 0x02
56
57 #define HBURST_SINGLE 0x00
58 #define HBURST_INCR 0x01
59 #define HBURST_INCR4 0x02
60 #define HBURST_INCR8 0x03
61
62 #define HPROT_DATA_CACHE BIT(0)
63 #define HPROT_PRIVILIGED BIT(1)
64 #define HPROT_BUFFERABLE BIT(2)
65 #define HPROT_CACHABLE BIT(3)
66
67 #define DEFAULT_RX_COALESCE_NSECS 0
68 #define DEFAULT_GMAC_RXQ_ORDER 9
69 #define DEFAULT_GMAC_TXQ_ORDER 8
70 #define DEFAULT_RX_BUF_ORDER 11
71 #define DEFAULT_NAPI_WEIGHT 64
72 #define TX_MAX_FRAGS 16
73 #define TX_QUEUE_NUM 1 /* max: 6 */
74 #define RX_MAX_ALLOC_ORDER 2
75
76 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
77 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
78 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
79 GMAC0_SWTQ00_FIN_INT_BIT)
80 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
81
82 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
83 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
84 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
85
86 /**
87 * struct gmac_queue_page - page buffer per-page info
88 * @page: the page struct
89 * @mapping: the dma address handle
90 */
91 struct gmac_queue_page {
92 struct page *page;
93 dma_addr_t mapping;
94 };
95
96 struct gmac_txq {
97 struct gmac_txdesc *ring;
98 struct sk_buff **skb;
99 unsigned int cptr;
100 unsigned int noirq_packets;
101 };
102
103 struct gemini_ethernet;
104
105 struct gemini_ethernet_port {
106 u8 id; /* 0 or 1 */
107
108 struct gemini_ethernet *geth;
109 struct net_device *netdev;
110 struct device *dev;
111 void __iomem *dma_base;
112 void __iomem *gmac_base;
113 struct clk *pclk;
114 struct reset_control *reset;
115 int irq;
116 __le32 mac_addr[3];
117
118 void __iomem *rxq_rwptr;
119 struct gmac_rxdesc *rxq_ring;
120 unsigned int rxq_order;
121
122 struct napi_struct napi;
123 struct hrtimer rx_coalesce_timer;
124 unsigned int rx_coalesce_nsecs;
125 unsigned int freeq_refill;
126 struct gmac_txq txq[TX_QUEUE_NUM];
127 unsigned int txq_order;
128 unsigned int irq_every_tx_packets;
129
130 dma_addr_t rxq_dma_base;
131 dma_addr_t txq_dma_base;
132
133 unsigned int msg_enable;
134 spinlock_t config_lock; /* Locks config register */
135
136 struct u64_stats_sync tx_stats_syncp;
137 struct u64_stats_sync rx_stats_syncp;
138 struct u64_stats_sync ir_stats_syncp;
139
140 struct rtnl_link_stats64 stats;
141 u64 hw_stats[RX_STATS_NUM];
142 u64 rx_stats[RX_STATUS_NUM];
143 u64 rx_csum_stats[RX_CHKSUM_NUM];
144 u64 rx_napi_exits;
145 u64 tx_frag_stats[TX_MAX_FRAGS];
146 u64 tx_frags_linearized;
147 u64 tx_hw_csummed;
148 };
149
150 struct gemini_ethernet {
151 struct device *dev;
152 void __iomem *base;
153 struct gemini_ethernet_port *port0;
154 struct gemini_ethernet_port *port1;
155 bool initialized;
156
157 spinlock_t irq_lock; /* Locks IRQ-related registers */
158 unsigned int freeq_order;
159 unsigned int freeq_frag_order;
160 struct gmac_rxdesc *freeq_ring;
161 dma_addr_t freeq_dma_base;
162 struct gmac_queue_page *freeq_pages;
163 unsigned int num_freeq_pages;
164 spinlock_t freeq_lock; /* Locks queue from reentrance */
165 };
166
167 #define GMAC_STATS_NUM ( \
168 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
169 TX_MAX_FRAGS + 2)
170
171 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
172 "GMAC_IN_DISCARDS",
173 "GMAC_IN_ERRORS",
174 "GMAC_IN_MCAST",
175 "GMAC_IN_BCAST",
176 "GMAC_IN_MAC1",
177 "GMAC_IN_MAC2",
178 "RX_STATUS_GOOD_FRAME",
179 "RX_STATUS_TOO_LONG_GOOD_CRC",
180 "RX_STATUS_RUNT_FRAME",
181 "RX_STATUS_SFD_NOT_FOUND",
182 "RX_STATUS_CRC_ERROR",
183 "RX_STATUS_TOO_LONG_BAD_CRC",
184 "RX_STATUS_ALIGNMENT_ERROR",
185 "RX_STATUS_TOO_LONG_BAD_ALIGN",
186 "RX_STATUS_RX_ERR",
187 "RX_STATUS_DA_FILTERED",
188 "RX_STATUS_BUFFER_FULL",
189 "RX_STATUS_11",
190 "RX_STATUS_12",
191 "RX_STATUS_13",
192 "RX_STATUS_14",
193 "RX_STATUS_15",
194 "RX_CHKSUM_IP_UDP_TCP_OK",
195 "RX_CHKSUM_IP_OK_ONLY",
196 "RX_CHKSUM_NONE",
197 "RX_CHKSUM_3",
198 "RX_CHKSUM_IP_ERR_UNKNOWN",
199 "RX_CHKSUM_IP_ERR",
200 "RX_CHKSUM_TCP_UDP_ERR",
201 "RX_CHKSUM_7",
202 "RX_NAPI_EXITS",
203 "TX_FRAGS[1]",
204 "TX_FRAGS[2]",
205 "TX_FRAGS[3]",
206 "TX_FRAGS[4]",
207 "TX_FRAGS[5]",
208 "TX_FRAGS[6]",
209 "TX_FRAGS[7]",
210 "TX_FRAGS[8]",
211 "TX_FRAGS[9]",
212 "TX_FRAGS[10]",
213 "TX_FRAGS[11]",
214 "TX_FRAGS[12]",
215 "TX_FRAGS[13]",
216 "TX_FRAGS[14]",
217 "TX_FRAGS[15]",
218 "TX_FRAGS[16+]",
219 "TX_FRAGS_LINEARIZED",
220 "TX_HW_CSUMMED",
221 };
222
223 static void gmac_dump_dma_state(struct net_device *netdev);
224
gmac_update_config0_reg(struct net_device *netdev, u32 val, u32 vmask)225 static void gmac_update_config0_reg(struct net_device *netdev,
226 u32 val, u32 vmask)
227 {
228 struct gemini_ethernet_port *port = netdev_priv(netdev);
229 unsigned long flags;
230 u32 reg;
231
232 spin_lock_irqsave(&port->config_lock, flags);
233
234 reg = readl(port->gmac_base + GMAC_CONFIG0);
235 reg = (reg & ~vmask) | val;
236 writel(reg, port->gmac_base + GMAC_CONFIG0);
237
238 spin_unlock_irqrestore(&port->config_lock, flags);
239 }
240
gmac_enable_tx_rx(struct net_device *netdev)241 static void gmac_enable_tx_rx(struct net_device *netdev)
242 {
243 struct gemini_ethernet_port *port = netdev_priv(netdev);
244 unsigned long flags;
245 u32 reg;
246
247 spin_lock_irqsave(&port->config_lock, flags);
248
249 reg = readl(port->gmac_base + GMAC_CONFIG0);
250 reg &= ~CONFIG0_TX_RX_DISABLE;
251 writel(reg, port->gmac_base + GMAC_CONFIG0);
252
253 spin_unlock_irqrestore(&port->config_lock, flags);
254 }
255
gmac_disable_tx_rx(struct net_device *netdev)256 static void gmac_disable_tx_rx(struct net_device *netdev)
257 {
258 struct gemini_ethernet_port *port = netdev_priv(netdev);
259 unsigned long flags;
260 u32 val;
261
262 spin_lock_irqsave(&port->config_lock, flags);
263
264 val = readl(port->gmac_base + GMAC_CONFIG0);
265 val |= CONFIG0_TX_RX_DISABLE;
266 writel(val, port->gmac_base + GMAC_CONFIG0);
267
268 spin_unlock_irqrestore(&port->config_lock, flags);
269
270 mdelay(10); /* let GMAC consume packet */
271 }
272
gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)273 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
274 {
275 struct gemini_ethernet_port *port = netdev_priv(netdev);
276 unsigned long flags;
277 u32 val;
278
279 spin_lock_irqsave(&port->config_lock, flags);
280
281 val = readl(port->gmac_base + GMAC_CONFIG0);
282 val &= ~CONFIG0_FLOW_CTL;
283 if (tx)
284 val |= CONFIG0_FLOW_TX;
285 if (rx)
286 val |= CONFIG0_FLOW_RX;
287 writel(val, port->gmac_base + GMAC_CONFIG0);
288
289 spin_unlock_irqrestore(&port->config_lock, flags);
290 }
291
gmac_speed_set(struct net_device *netdev)292 static void gmac_speed_set(struct net_device *netdev)
293 {
294 struct gemini_ethernet_port *port = netdev_priv(netdev);
295 struct phy_device *phydev = netdev->phydev;
296 union gmac_status status, old_status;
297 int pause_tx = 0;
298 int pause_rx = 0;
299
300 status.bits32 = readl(port->gmac_base + GMAC_STATUS);
301 old_status.bits32 = status.bits32;
302 status.bits.link = phydev->link;
303 status.bits.duplex = phydev->duplex;
304
305 switch (phydev->speed) {
306 case 1000:
307 status.bits.speed = GMAC_SPEED_1000;
308 if (phy_interface_mode_is_rgmii(phydev->interface))
309 status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
310 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n",
311 phydev_name(phydev));
312 break;
313 case 100:
314 status.bits.speed = GMAC_SPEED_100;
315 if (phy_interface_mode_is_rgmii(phydev->interface))
316 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
317 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n",
318 phydev_name(phydev));
319 break;
320 case 10:
321 status.bits.speed = GMAC_SPEED_10;
322 if (phy_interface_mode_is_rgmii(phydev->interface))
323 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
324 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n",
325 phydev_name(phydev));
326 break;
327 default:
328 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n",
329 phydev->speed, phydev_name(phydev));
330 }
331
332 if (phydev->duplex == DUPLEX_FULL) {
333 u16 lcladv = phy_read(phydev, MII_ADVERTISE);
334 u16 rmtadv = phy_read(phydev, MII_LPA);
335 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
336
337 if (cap & FLOW_CTRL_RX)
338 pause_rx = 1;
339 if (cap & FLOW_CTRL_TX)
340 pause_tx = 1;
341 }
342
343 gmac_set_flow_control(netdev, pause_tx, pause_rx);
344
345 if (old_status.bits32 == status.bits32)
346 return;
347
348 if (netif_msg_link(port)) {
349 phy_print_status(phydev);
350 netdev_info(netdev, "link flow control: %s\n",
351 phydev->pause
352 ? (phydev->asym_pause ? "tx" : "both")
353 : (phydev->asym_pause ? "rx" : "none")
354 );
355 }
356
357 gmac_disable_tx_rx(netdev);
358 writel(status.bits32, port->gmac_base + GMAC_STATUS);
359 gmac_enable_tx_rx(netdev);
360 }
361
gmac_setup_phy(struct net_device *netdev)362 static int gmac_setup_phy(struct net_device *netdev)
363 {
364 struct gemini_ethernet_port *port = netdev_priv(netdev);
365 union gmac_status status = { .bits32 = 0 };
366 struct device *dev = port->dev;
367 struct phy_device *phy;
368
369 phy = of_phy_get_and_connect(netdev,
370 dev->of_node,
371 gmac_speed_set);
372 if (!phy)
373 return -ENODEV;
374 netdev->phydev = phy;
375
376 phy_set_max_speed(phy, SPEED_1000);
377 phy_support_asym_pause(phy);
378
379 /* set PHY interface type */
380 switch (phy->interface) {
381 case PHY_INTERFACE_MODE_MII:
382 netdev_dbg(netdev,
383 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n");
384 status.bits.mii_rmii = GMAC_PHY_MII;
385 break;
386 case PHY_INTERFACE_MODE_GMII:
387 netdev_dbg(netdev,
388 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n");
389 status.bits.mii_rmii = GMAC_PHY_GMII;
390 break;
391 case PHY_INTERFACE_MODE_RGMII:
392 case PHY_INTERFACE_MODE_RGMII_ID:
393 case PHY_INTERFACE_MODE_RGMII_TXID:
394 case PHY_INTERFACE_MODE_RGMII_RXID:
395 netdev_dbg(netdev,
396 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n");
397 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
398 break;
399 default:
400 netdev_err(netdev, "Unsupported MII interface\n");
401 phy_disconnect(phy);
402 netdev->phydev = NULL;
403 return -EINVAL;
404 }
405 writel(status.bits32, port->gmac_base + GMAC_STATUS);
406
407 if (netif_msg_link(port))
408 phy_attached_info(phy);
409
410 return 0;
411 }
412
413 /* The maximum frame length is not logically enumerated in the
414 * hardware, so we do a table lookup to find the applicable max
415 * frame length.
416 */
417 struct gmac_max_framelen {
418 unsigned int max_l3_len;
419 u8 val;
420 };
421
422 static const struct gmac_max_framelen gmac_maxlens[] = {
423 {
424 .max_l3_len = 1518,
425 .val = CONFIG0_MAXLEN_1518,
426 },
427 {
428 .max_l3_len = 1522,
429 .val = CONFIG0_MAXLEN_1522,
430 },
431 {
432 .max_l3_len = 1536,
433 .val = CONFIG0_MAXLEN_1536,
434 },
435 {
436 .max_l3_len = 1548,
437 .val = CONFIG0_MAXLEN_1548,
438 },
439 {
440 .max_l3_len = 9212,
441 .val = CONFIG0_MAXLEN_9k,
442 },
443 {
444 .max_l3_len = 10236,
445 .val = CONFIG0_MAXLEN_10k,
446 },
447 };
448
gmac_pick_rx_max_len(unsigned int max_l3_len)449 static int gmac_pick_rx_max_len(unsigned int max_l3_len)
450 {
451 const struct gmac_max_framelen *maxlen;
452 int maxtot;
453 int i;
454
455 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN;
456
457 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) {
458 maxlen = &gmac_maxlens[i];
459 if (maxtot <= maxlen->max_l3_len)
460 return maxlen->val;
461 }
462
463 return -1;
464 }
465
gmac_init(struct net_device *netdev)466 static int gmac_init(struct net_device *netdev)
467 {
468 struct gemini_ethernet_port *port = netdev_priv(netdev);
469 union gmac_config0 config0 = { .bits = {
470 .dis_tx = 1,
471 .dis_rx = 1,
472 .ipv4_rx_chksum = 1,
473 .ipv6_rx_chksum = 1,
474 .rx_err_detect = 1,
475 .rgmm_edge = 1,
476 .port0_chk_hwq = 1,
477 .port1_chk_hwq = 1,
478 .port0_chk_toeq = 1,
479 .port1_chk_toeq = 1,
480 .port0_chk_classq = 1,
481 .port1_chk_classq = 1,
482 } };
483 union gmac_ahb_weight ahb_weight = { .bits = {
484 .rx_weight = 1,
485 .tx_weight = 1,
486 .hash_weight = 1,
487 .pre_req = 0x1f,
488 .tq_dv_threshold = 0,
489 } };
490 union gmac_tx_wcr0 hw_weigh = { .bits = {
491 .hw_tq3 = 1,
492 .hw_tq2 = 1,
493 .hw_tq1 = 1,
494 .hw_tq0 = 1,
495 } };
496 union gmac_tx_wcr1 sw_weigh = { .bits = {
497 .sw_tq5 = 1,
498 .sw_tq4 = 1,
499 .sw_tq3 = 1,
500 .sw_tq2 = 1,
501 .sw_tq1 = 1,
502 .sw_tq0 = 1,
503 } };
504 union gmac_config1 config1 = { .bits = {
505 .set_threshold = 16,
506 .rel_threshold = 24,
507 } };
508 union gmac_config2 config2 = { .bits = {
509 .set_threshold = 16,
510 .rel_threshold = 32,
511 } };
512 union gmac_config3 config3 = { .bits = {
513 .set_threshold = 0,
514 .rel_threshold = 0,
515 } };
516 union gmac_config0 tmp;
517
518 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
519 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
520 config0.bits.reserved = tmp.bits.reserved;
521 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
522 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
523 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
524 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
525
526 readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
527 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
528
529 writel(hw_weigh.bits32,
530 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
531 writel(sw_weigh.bits32,
532 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
533
534 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
535 port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
536 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
537
538 /* Mark every quarter of the queue a packet for interrupt
539 * in order to be able to wake up the queue if it was stopped
540 */
541 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
542
543 return 0;
544 }
545
gmac_setup_txqs(struct net_device *netdev)546 static int gmac_setup_txqs(struct net_device *netdev)
547 {
548 struct gemini_ethernet_port *port = netdev_priv(netdev);
549 unsigned int n_txq = netdev->num_tx_queues;
550 struct gemini_ethernet *geth = port->geth;
551 size_t entries = 1 << port->txq_order;
552 struct gmac_txq *txq = port->txq;
553 struct gmac_txdesc *desc_ring;
554 size_t len = n_txq * entries;
555 struct sk_buff **skb_tab;
556 void __iomem *rwptr_reg;
557 unsigned int r;
558 int i;
559
560 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
561
562 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
563 if (!skb_tab)
564 return -ENOMEM;
565
566 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
567 &port->txq_dma_base, GFP_KERNEL);
568
569 if (!desc_ring) {
570 kfree(skb_tab);
571 return -ENOMEM;
572 }
573
574 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
575 dev_warn(geth->dev, "TX queue base is not aligned\n");
576 dma_free_coherent(geth->dev, len * sizeof(*desc_ring),
577 desc_ring, port->txq_dma_base);
578 kfree(skb_tab);
579 return -ENOMEM;
580 }
581
582 writel(port->txq_dma_base | port->txq_order,
583 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
584
585 for (i = 0; i < n_txq; i++) {
586 txq->ring = desc_ring;
587 txq->skb = skb_tab;
588 txq->noirq_packets = 0;
589
590 r = readw(rwptr_reg);
591 rwptr_reg += 2;
592 writew(r, rwptr_reg);
593 rwptr_reg += 2;
594 txq->cptr = r;
595
596 txq++;
597 desc_ring += entries;
598 skb_tab += entries;
599 }
600
601 return 0;
602 }
603
gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq, unsigned int r)604 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
605 unsigned int r)
606 {
607 struct gemini_ethernet_port *port = netdev_priv(netdev);
608 unsigned int m = (1 << port->txq_order) - 1;
609 struct gemini_ethernet *geth = port->geth;
610 unsigned int c = txq->cptr;
611 union gmac_txdesc_0 word0;
612 union gmac_txdesc_1 word1;
613 unsigned int hwchksum = 0;
614 unsigned long bytes = 0;
615 struct gmac_txdesc *txd;
616 unsigned short nfrags;
617 unsigned int errs = 0;
618 unsigned int pkts = 0;
619 unsigned int word3;
620 dma_addr_t mapping;
621
622 if (c == r)
623 return;
624
625 while (c != r) {
626 txd = txq->ring + c;
627 word0 = txd->word0;
628 word1 = txd->word1;
629 mapping = txd->word2.buf_adr;
630 word3 = txd->word3.bits32;
631
632 dma_unmap_single(geth->dev, mapping,
633 word0.bits.buffer_size, DMA_TO_DEVICE);
634
635 if (word3 & EOF_BIT)
636 dev_kfree_skb(txq->skb[c]);
637
638 c++;
639 c &= m;
640
641 if (!(word3 & SOF_BIT))
642 continue;
643
644 if (!word0.bits.status_tx_ok) {
645 errs++;
646 continue;
647 }
648
649 pkts++;
650 bytes += txd->word1.bits.byte_count;
651
652 if (word1.bits32 & TSS_CHECKUM_ENABLE)
653 hwchksum++;
654
655 nfrags = word0.bits.desc_count - 1;
656 if (nfrags) {
657 if (nfrags >= TX_MAX_FRAGS)
658 nfrags = TX_MAX_FRAGS - 1;
659
660 u64_stats_update_begin(&port->tx_stats_syncp);
661 port->tx_frag_stats[nfrags]++;
662 u64_stats_update_end(&port->tx_stats_syncp);
663 }
664 }
665
666 u64_stats_update_begin(&port->ir_stats_syncp);
667 port->stats.tx_errors += errs;
668 port->stats.tx_packets += pkts;
669 port->stats.tx_bytes += bytes;
670 port->tx_hw_csummed += hwchksum;
671 u64_stats_update_end(&port->ir_stats_syncp);
672
673 txq->cptr = c;
674 }
675
gmac_cleanup_txqs(struct net_device *netdev)676 static void gmac_cleanup_txqs(struct net_device *netdev)
677 {
678 struct gemini_ethernet_port *port = netdev_priv(netdev);
679 unsigned int n_txq = netdev->num_tx_queues;
680 struct gemini_ethernet *geth = port->geth;
681 void __iomem *rwptr_reg;
682 unsigned int r, i;
683
684 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
685
686 for (i = 0; i < n_txq; i++) {
687 r = readw(rwptr_reg);
688 rwptr_reg += 2;
689 writew(r, rwptr_reg);
690 rwptr_reg += 2;
691
692 gmac_clean_txq(netdev, port->txq + i, r);
693 }
694 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
695
696 kfree(port->txq->skb);
697 dma_free_coherent(geth->dev,
698 n_txq * sizeof(*port->txq->ring) << port->txq_order,
699 port->txq->ring, port->txq_dma_base);
700 }
701
gmac_setup_rxq(struct net_device *netdev)702 static int gmac_setup_rxq(struct net_device *netdev)
703 {
704 struct gemini_ethernet_port *port = netdev_priv(netdev);
705 struct gemini_ethernet *geth = port->geth;
706 struct nontoe_qhdr __iomem *qhdr;
707
708 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
709 port->rxq_rwptr = &qhdr->word1;
710
711 /* Remap a slew of memory to use for the RX queue */
712 port->rxq_ring = dma_alloc_coherent(geth->dev,
713 sizeof(*port->rxq_ring) << port->rxq_order,
714 &port->rxq_dma_base, GFP_KERNEL);
715 if (!port->rxq_ring)
716 return -ENOMEM;
717 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
718 dev_warn(geth->dev, "RX queue base is not aligned\n");
719 return -ENOMEM;
720 }
721
722 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
723 writel(0, port->rxq_rwptr);
724 return 0;
725 }
726
727 static struct gmac_queue_page *
gmac_get_queue_page(struct gemini_ethernet *geth, struct gemini_ethernet_port *port, dma_addr_t addr)728 gmac_get_queue_page(struct gemini_ethernet *geth,
729 struct gemini_ethernet_port *port,
730 dma_addr_t addr)
731 {
732 struct gmac_queue_page *gpage;
733 dma_addr_t mapping;
734 int i;
735
736 /* Only look for even pages */
737 mapping = addr & PAGE_MASK;
738
739 if (!geth->freeq_pages) {
740 dev_err(geth->dev, "try to get page with no page list\n");
741 return NULL;
742 }
743
744 /* Look up a ring buffer page from virtual mapping */
745 for (i = 0; i < geth->num_freeq_pages; i++) {
746 gpage = &geth->freeq_pages[i];
747 if (gpage->mapping == mapping)
748 return gpage;
749 }
750
751 return NULL;
752 }
753
gmac_cleanup_rxq(struct net_device *netdev)754 static void gmac_cleanup_rxq(struct net_device *netdev)
755 {
756 struct gemini_ethernet_port *port = netdev_priv(netdev);
757 struct gemini_ethernet *geth = port->geth;
758 struct gmac_rxdesc *rxd = port->rxq_ring;
759 static struct gmac_queue_page *gpage;
760 struct nontoe_qhdr __iomem *qhdr;
761 void __iomem *dma_reg;
762 void __iomem *ptr_reg;
763 dma_addr_t mapping;
764 union dma_rwptr rw;
765 unsigned int r, w;
766
767 qhdr = geth->base +
768 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
769 dma_reg = &qhdr->word0;
770 ptr_reg = &qhdr->word1;
771
772 rw.bits32 = readl(ptr_reg);
773 r = rw.bits.rptr;
774 w = rw.bits.wptr;
775 writew(r, ptr_reg + 2);
776
777 writel(0, dma_reg);
778
779 /* Loop from read pointer to write pointer of the RX queue
780 * and free up all pages by the queue.
781 */
782 while (r != w) {
783 mapping = rxd[r].word2.buf_adr;
784 r++;
785 r &= ((1 << port->rxq_order) - 1);
786
787 if (!mapping)
788 continue;
789
790 /* Freeq pointers are one page off */
791 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
792 if (!gpage) {
793 dev_err(geth->dev, "could not find page\n");
794 continue;
795 }
796 /* Release the RX queue reference to the page */
797 put_page(gpage->page);
798 }
799
800 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
801 port->rxq_ring, port->rxq_dma_base);
802 }
803
geth_freeq_alloc_map_page(struct gemini_ethernet *geth, int pn)804 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
805 int pn)
806 {
807 struct gmac_rxdesc *freeq_entry;
808 struct gmac_queue_page *gpage;
809 unsigned int fpp_order;
810 unsigned int frag_len;
811 dma_addr_t mapping;
812 struct page *page;
813 int i;
814
815 /* First allocate and DMA map a single page */
816 page = alloc_page(GFP_ATOMIC);
817 if (!page)
818 return NULL;
819
820 mapping = dma_map_single(geth->dev, page_address(page),
821 PAGE_SIZE, DMA_FROM_DEVICE);
822 if (dma_mapping_error(geth->dev, mapping)) {
823 put_page(page);
824 return NULL;
825 }
826
827 /* The assign the page mapping (physical address) to the buffer address
828 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
829 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
830 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
831 * each page normally needs two entries in the queue.
832 */
833 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
834 fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
835 freeq_entry = geth->freeq_ring + (pn << fpp_order);
836 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
837 pn, frag_len, (1 << fpp_order), freeq_entry);
838 for (i = (1 << fpp_order); i > 0; i--) {
839 freeq_entry->word2.buf_adr = mapping;
840 freeq_entry++;
841 mapping += frag_len;
842 }
843
844 /* If the freeq entry already has a page mapped, then unmap it. */
845 gpage = &geth->freeq_pages[pn];
846 if (gpage->page) {
847 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
848 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
849 /* This should be the last reference to the page so it gets
850 * released
851 */
852 put_page(gpage->page);
853 }
854
855 /* Then put our new mapping into the page table */
856 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
857 pn, (unsigned int)mapping, page);
858 gpage->mapping = mapping;
859 gpage->page = page;
860
861 return page;
862 }
863
864 /**
865 * geth_fill_freeq() - Fill the freeq with empty fragments to use
866 * @geth: the ethernet adapter
867 * @refill: whether to reset the queue by filling in all freeq entries or
868 * just refill it, usually the interrupt to refill the queue happens when
869 * the queue is half empty.
870 */
geth_fill_freeq(struct gemini_ethernet *geth, bool refill)871 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
872 {
873 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
874 unsigned int count = 0;
875 unsigned int pn, epn;
876 unsigned long flags;
877 union dma_rwptr rw;
878 unsigned int m_pn;
879
880 /* Mask for page */
881 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
882
883 spin_lock_irqsave(&geth->freeq_lock, flags);
884
885 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
886 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
887 epn = (rw.bits.rptr >> fpp_order) - 1;
888 epn &= m_pn;
889
890 /* Loop over the freeq ring buffer entries */
891 while (pn != epn) {
892 struct gmac_queue_page *gpage;
893 struct page *page;
894
895 gpage = &geth->freeq_pages[pn];
896 page = gpage->page;
897
898 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
899 pn, page_ref_count(page), 1 << fpp_order);
900
901 if (page_ref_count(page) > 1) {
902 unsigned int fl = (pn - epn) & m_pn;
903
904 if (fl > 64 >> fpp_order)
905 break;
906
907 page = geth_freeq_alloc_map_page(geth, pn);
908 if (!page)
909 break;
910 }
911
912 /* Add one reference per fragment in the page */
913 page_ref_add(page, 1 << fpp_order);
914 count += 1 << fpp_order;
915 pn++;
916 pn &= m_pn;
917 }
918
919 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
920
921 spin_unlock_irqrestore(&geth->freeq_lock, flags);
922
923 return count;
924 }
925
geth_setup_freeq(struct gemini_ethernet *geth)926 static int geth_setup_freeq(struct gemini_ethernet *geth)
927 {
928 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
929 unsigned int frag_len = 1 << geth->freeq_frag_order;
930 unsigned int len = 1 << geth->freeq_order;
931 unsigned int pages = len >> fpp_order;
932 union queue_threshold qt;
933 union dma_skb_size skbsz;
934 unsigned int filled;
935 unsigned int pn;
936
937 geth->freeq_ring = dma_alloc_coherent(geth->dev,
938 sizeof(*geth->freeq_ring) << geth->freeq_order,
939 &geth->freeq_dma_base, GFP_KERNEL);
940 if (!geth->freeq_ring)
941 return -ENOMEM;
942 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
943 dev_warn(geth->dev, "queue ring base is not aligned\n");
944 goto err_freeq;
945 }
946
947 /* Allocate a mapping to page look-up index */
948 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages),
949 GFP_KERNEL);
950 if (!geth->freeq_pages)
951 goto err_freeq;
952 geth->num_freeq_pages = pages;
953
954 dev_info(geth->dev, "allocate %d pages for queue\n", pages);
955 for (pn = 0; pn < pages; pn++)
956 if (!geth_freeq_alloc_map_page(geth, pn))
957 goto err_freeq_alloc;
958
959 filled = geth_fill_freeq(geth, false);
960 if (!filled)
961 goto err_freeq_alloc;
962
963 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
964 qt.bits.swfq_empty = 32;
965 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
966
967 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
968 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
969 writel(geth->freeq_dma_base | geth->freeq_order,
970 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
971
972 return 0;
973
974 err_freeq_alloc:
975 while (pn > 0) {
976 struct gmac_queue_page *gpage;
977 dma_addr_t mapping;
978
979 --pn;
980 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
981 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
982 gpage = &geth->freeq_pages[pn];
983 put_page(gpage->page);
984 }
985
986 kfree(geth->freeq_pages);
987 err_freeq:
988 dma_free_coherent(geth->dev,
989 sizeof(*geth->freeq_ring) << geth->freeq_order,
990 geth->freeq_ring, geth->freeq_dma_base);
991 geth->freeq_ring = NULL;
992 return -ENOMEM;
993 }
994
995 /**
996 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
997 * @geth: the Gemini global ethernet state
998 */
geth_cleanup_freeq(struct gemini_ethernet *geth)999 static void geth_cleanup_freeq(struct gemini_ethernet *geth)
1000 {
1001 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
1002 unsigned int frag_len = 1 << geth->freeq_frag_order;
1003 unsigned int len = 1 << geth->freeq_order;
1004 unsigned int pages = len >> fpp_order;
1005 unsigned int pn;
1006
1007 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
1008 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
1009 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1010
1011 for (pn = 0; pn < pages; pn++) {
1012 struct gmac_queue_page *gpage;
1013 dma_addr_t mapping;
1014
1015 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
1016 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
1017
1018 gpage = &geth->freeq_pages[pn];
1019 while (page_ref_count(gpage->page) > 0)
1020 put_page(gpage->page);
1021 }
1022
1023 kfree(geth->freeq_pages);
1024
1025 dma_free_coherent(geth->dev,
1026 sizeof(*geth->freeq_ring) << geth->freeq_order,
1027 geth->freeq_ring, geth->freeq_dma_base);
1028 }
1029
1030 /**
1031 * geth_resize_freeq() - resize the software queue depth
1032 * @port: the port requesting the change
1033 *
1034 * This gets called at least once during probe() so the device queue gets
1035 * "resized" from the hardware defaults. Since both ports/net devices share
1036 * the same hardware queue, some synchronization between the ports is
1037 * needed.
1038 */
geth_resize_freeq(struct gemini_ethernet_port *port)1039 static int geth_resize_freeq(struct gemini_ethernet_port *port)
1040 {
1041 struct gemini_ethernet *geth = port->geth;
1042 struct net_device *netdev = port->netdev;
1043 struct gemini_ethernet_port *other_port;
1044 struct net_device *other_netdev;
1045 unsigned int new_size = 0;
1046 unsigned int new_order;
1047 unsigned long flags;
1048 u32 en;
1049 int ret;
1050
1051 if (netdev->dev_id == 0)
1052 other_netdev = geth->port1->netdev;
1053 else
1054 other_netdev = geth->port0->netdev;
1055
1056 if (other_netdev && netif_running(other_netdev))
1057 return -EBUSY;
1058
1059 new_size = 1 << (port->rxq_order + 1);
1060 netdev_dbg(netdev, "port %d size: %d order %d\n",
1061 netdev->dev_id,
1062 new_size,
1063 port->rxq_order);
1064 if (other_netdev) {
1065 other_port = netdev_priv(other_netdev);
1066 new_size += 1 << (other_port->rxq_order + 1);
1067 netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1068 other_netdev->dev_id,
1069 (1 << (other_port->rxq_order + 1)),
1070 other_port->rxq_order);
1071 }
1072
1073 new_order = min(15, ilog2(new_size - 1) + 1);
1074 dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1075 new_size, new_order);
1076 if (geth->freeq_order == new_order)
1077 return 0;
1078
1079 spin_lock_irqsave(&geth->irq_lock, flags);
1080
1081 /* Disable the software queue IRQs */
1082 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1083 en &= ~SWFQ_EMPTY_INT_BIT;
1084 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1085 spin_unlock_irqrestore(&geth->irq_lock, flags);
1086
1087 /* Drop the old queue */
1088 if (geth->freeq_ring)
1089 geth_cleanup_freeq(geth);
1090
1091 /* Allocate a new queue with the desired order */
1092 geth->freeq_order = new_order;
1093 ret = geth_setup_freeq(geth);
1094
1095 /* Restart the interrupts - NOTE if this is the first resize
1096 * after probe(), this is where the interrupts get turned on
1097 * in the first place.
1098 */
1099 spin_lock_irqsave(&geth->irq_lock, flags);
1100 en |= SWFQ_EMPTY_INT_BIT;
1101 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1102 spin_unlock_irqrestore(&geth->irq_lock, flags);
1103
1104 return ret;
1105 }
1106
gmac_tx_irq_enable(struct net_device *netdev, unsigned int txq, int en)1107 static void gmac_tx_irq_enable(struct net_device *netdev,
1108 unsigned int txq, int en)
1109 {
1110 struct gemini_ethernet_port *port = netdev_priv(netdev);
1111 struct gemini_ethernet *geth = port->geth;
1112 u32 val, mask;
1113
1114 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1115
1116 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1117
1118 if (en)
1119 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1120
1121 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1122 val = en ? val | mask : val & ~mask;
1123 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1124 }
1125
gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)1126 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1127 {
1128 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1129
1130 gmac_tx_irq_enable(netdev, txq_num, 0);
1131 netif_tx_wake_queue(ntxq);
1132 }
1133
gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, struct gmac_txq *txq, unsigned short *desc)1134 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1135 struct gmac_txq *txq, unsigned short *desc)
1136 {
1137 struct gemini_ethernet_port *port = netdev_priv(netdev);
1138 struct skb_shared_info *skb_si = skb_shinfo(skb);
1139 unsigned short m = (1 << port->txq_order) - 1;
1140 short frag, last_frag = skb_si->nr_frags - 1;
1141 struct gemini_ethernet *geth = port->geth;
1142 unsigned int word1, word3, buflen;
1143 unsigned short w = *desc;
1144 struct gmac_txdesc *txd;
1145 skb_frag_t *skb_frag;
1146 dma_addr_t mapping;
1147 unsigned short mtu;
1148 void *buffer;
1149 int ret;
1150
1151 mtu = ETH_HLEN;
1152 mtu += netdev->mtu;
1153 if (skb->protocol == htons(ETH_P_8021Q))
1154 mtu += VLAN_HLEN;
1155
1156 word1 = skb->len;
1157 word3 = SOF_BIT;
1158
1159 if (word1 > mtu) {
1160 word1 |= TSS_MTU_ENABLE_BIT;
1161 word3 |= mtu;
1162 }
1163
1164 if (skb->len >= ETH_FRAME_LEN) {
1165 /* Hardware offloaded checksumming isn't working on frames
1166 * bigger than 1514 bytes. A hypothesis about this is that the
1167 * checksum buffer is only 1518 bytes, so when the frames get
1168 * bigger they get truncated, or the last few bytes get
1169 * overwritten by the FCS.
1170 *
1171 * Just use software checksumming and bypass on bigger frames.
1172 */
1173 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1174 ret = skb_checksum_help(skb);
1175 if (ret)
1176 return ret;
1177 }
1178 word1 |= TSS_BYPASS_BIT;
1179 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1180 int tcp = 0;
1181
1182 /* We do not switch off the checksumming on non TCP/UDP
1183 * frames: as is shown from tests, the checksumming engine
1184 * is smart enough to see that a frame is not actually TCP
1185 * or UDP and then just pass it through without any changes
1186 * to the frame.
1187 */
1188 if (skb->protocol == htons(ETH_P_IP)) {
1189 word1 |= TSS_IP_CHKSUM_BIT;
1190 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1191 } else { /* IPv6 */
1192 word1 |= TSS_IPV6_ENABLE_BIT;
1193 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1194 }
1195
1196 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1197 }
1198
1199 frag = -1;
1200 while (frag <= last_frag) {
1201 if (frag == -1) {
1202 buffer = skb->data;
1203 buflen = skb_headlen(skb);
1204 } else {
1205 skb_frag = skb_si->frags + frag;
1206 buffer = skb_frag_address(skb_frag);
1207 buflen = skb_frag_size(skb_frag);
1208 }
1209
1210 if (frag == last_frag) {
1211 word3 |= EOF_BIT;
1212 txq->skb[w] = skb;
1213 }
1214
1215 mapping = dma_map_single(geth->dev, buffer, buflen,
1216 DMA_TO_DEVICE);
1217 if (dma_mapping_error(geth->dev, mapping))
1218 goto map_error;
1219
1220 txd = txq->ring + w;
1221 txd->word0.bits32 = buflen;
1222 txd->word1.bits32 = word1;
1223 txd->word2.buf_adr = mapping;
1224 txd->word3.bits32 = word3;
1225
1226 word3 &= MTU_SIZE_BIT_MASK;
1227 w++;
1228 w &= m;
1229 frag++;
1230 }
1231
1232 *desc = w;
1233 return 0;
1234
1235 map_error:
1236 while (w != *desc) {
1237 w--;
1238 w &= m;
1239
1240 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1241 txq->ring[w].word0.bits.buffer_size,
1242 DMA_TO_DEVICE);
1243 }
1244 return -ENOMEM;
1245 }
1246
gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)1247 static netdev_tx_t gmac_start_xmit(struct sk_buff *skb,
1248 struct net_device *netdev)
1249 {
1250 struct gemini_ethernet_port *port = netdev_priv(netdev);
1251 unsigned short m = (1 << port->txq_order) - 1;
1252 struct netdev_queue *ntxq;
1253 unsigned short r, w, d;
1254 void __iomem *ptr_reg;
1255 struct gmac_txq *txq;
1256 int txq_num, nfrags;
1257 union dma_rwptr rw;
1258
1259 if (skb->len >= 0x10000)
1260 goto out_drop_free;
1261
1262 txq_num = skb_get_queue_mapping(skb);
1263 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1264 txq = &port->txq[txq_num];
1265 ntxq = netdev_get_tx_queue(netdev, txq_num);
1266 nfrags = skb_shinfo(skb)->nr_frags;
1267
1268 rw.bits32 = readl(ptr_reg);
1269 r = rw.bits.rptr;
1270 w = rw.bits.wptr;
1271
1272 d = txq->cptr - w - 1;
1273 d &= m;
1274
1275 if (d < nfrags + 2) {
1276 gmac_clean_txq(netdev, txq, r);
1277 d = txq->cptr - w - 1;
1278 d &= m;
1279
1280 if (d < nfrags + 2) {
1281 netif_tx_stop_queue(ntxq);
1282
1283 d = txq->cptr + nfrags + 16;
1284 d &= m;
1285 txq->ring[d].word3.bits.eofie = 1;
1286 gmac_tx_irq_enable(netdev, txq_num, 1);
1287
1288 u64_stats_update_begin(&port->tx_stats_syncp);
1289 netdev->stats.tx_fifo_errors++;
1290 u64_stats_update_end(&port->tx_stats_syncp);
1291 return NETDEV_TX_BUSY;
1292 }
1293 }
1294
1295 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1296 if (skb_linearize(skb))
1297 goto out_drop;
1298
1299 u64_stats_update_begin(&port->tx_stats_syncp);
1300 port->tx_frags_linearized++;
1301 u64_stats_update_end(&port->tx_stats_syncp);
1302
1303 if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1304 goto out_drop_free;
1305 }
1306
1307 writew(w, ptr_reg + 2);
1308
1309 gmac_clean_txq(netdev, txq, r);
1310 return NETDEV_TX_OK;
1311
1312 out_drop_free:
1313 dev_kfree_skb(skb);
1314 out_drop:
1315 u64_stats_update_begin(&port->tx_stats_syncp);
1316 port->stats.tx_dropped++;
1317 u64_stats_update_end(&port->tx_stats_syncp);
1318 return NETDEV_TX_OK;
1319 }
1320
gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue)1321 static void gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1322 {
1323 netdev_err(netdev, "Tx timeout\n");
1324 gmac_dump_dma_state(netdev);
1325 }
1326
gmac_enable_irq(struct net_device *netdev, int enable)1327 static void gmac_enable_irq(struct net_device *netdev, int enable)
1328 {
1329 struct gemini_ethernet_port *port = netdev_priv(netdev);
1330 struct gemini_ethernet *geth = port->geth;
1331 unsigned long flags;
1332 u32 val, mask;
1333
1334 netdev_dbg(netdev, "%s device %d %s\n", __func__,
1335 netdev->dev_id, enable ? "enable" : "disable");
1336 spin_lock_irqsave(&geth->irq_lock, flags);
1337
1338 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1339 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1340 val = enable ? (val | mask) : (val & ~mask);
1341 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1342
1343 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1344 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1345 val = enable ? (val | mask) : (val & ~mask);
1346 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1347
1348 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1349 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1350 val = enable ? (val | mask) : (val & ~mask);
1351 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1352
1353 spin_unlock_irqrestore(&geth->irq_lock, flags);
1354 }
1355
gmac_enable_rx_irq(struct net_device *netdev, int enable)1356 static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1357 {
1358 struct gemini_ethernet_port *port = netdev_priv(netdev);
1359 struct gemini_ethernet *geth = port->geth;
1360 unsigned long flags;
1361 u32 val, mask;
1362
1363 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1364 enable ? "enable" : "disable");
1365 spin_lock_irqsave(&geth->irq_lock, flags);
1366 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1367
1368 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1369 val = enable ? (val | mask) : (val & ~mask);
1370 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1371
1372 spin_unlock_irqrestore(&geth->irq_lock, flags);
1373 }
1374
gmac_skb_if_good_frame(struct gemini_ethernet_port *port, union gmac_rxdesc_0 word0, unsigned int frame_len)1375 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1376 union gmac_rxdesc_0 word0,
1377 unsigned int frame_len)
1378 {
1379 unsigned int rx_csum = word0.bits.chksum_status;
1380 unsigned int rx_status = word0.bits.status;
1381 struct sk_buff *skb = NULL;
1382
1383 port->rx_stats[rx_status]++;
1384 port->rx_csum_stats[rx_csum]++;
1385
1386 if (word0.bits.derr || word0.bits.perr ||
1387 rx_status || frame_len < ETH_ZLEN ||
1388 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1389 port->stats.rx_errors++;
1390
1391 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1392 port->stats.rx_length_errors++;
1393 if (RX_ERROR_OVER(rx_status))
1394 port->stats.rx_over_errors++;
1395 if (RX_ERROR_CRC(rx_status))
1396 port->stats.rx_crc_errors++;
1397 if (RX_ERROR_FRAME(rx_status))
1398 port->stats.rx_frame_errors++;
1399 return NULL;
1400 }
1401
1402 skb = napi_get_frags(&port->napi);
1403 if (!skb)
1404 goto update_exit;
1405
1406 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1407 skb->ip_summed = CHECKSUM_UNNECESSARY;
1408
1409 update_exit:
1410 port->stats.rx_bytes += frame_len;
1411 port->stats.rx_packets++;
1412 return skb;
1413 }
1414
gmac_rx(struct net_device *netdev, unsigned int budget)1415 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1416 {
1417 struct gemini_ethernet_port *port = netdev_priv(netdev);
1418 unsigned short m = (1 << port->rxq_order) - 1;
1419 struct gemini_ethernet *geth = port->geth;
1420 void __iomem *ptr_reg = port->rxq_rwptr;
1421 unsigned int frame_len, frag_len;
1422 struct gmac_rxdesc *rx = NULL;
1423 struct gmac_queue_page *gpage;
1424 static struct sk_buff *skb;
1425 union gmac_rxdesc_0 word0;
1426 union gmac_rxdesc_1 word1;
1427 union gmac_rxdesc_3 word3;
1428 struct page *page = NULL;
1429 unsigned int page_offs;
1430 unsigned short r, w;
1431 union dma_rwptr rw;
1432 dma_addr_t mapping;
1433 int frag_nr = 0;
1434
1435 rw.bits32 = readl(ptr_reg);
1436 /* Reset interrupt as all packages until here are taken into account */
1437 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1438 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1439 r = rw.bits.rptr;
1440 w = rw.bits.wptr;
1441
1442 while (budget && w != r) {
1443 rx = port->rxq_ring + r;
1444 word0 = rx->word0;
1445 word1 = rx->word1;
1446 mapping = rx->word2.buf_adr;
1447 word3 = rx->word3;
1448
1449 r++;
1450 r &= m;
1451
1452 frag_len = word0.bits.buffer_size;
1453 frame_len = word1.bits.byte_count;
1454 page_offs = mapping & ~PAGE_MASK;
1455
1456 if (!mapping) {
1457 netdev_err(netdev,
1458 "rxq[%u]: HW BUG: zero DMA desc\n", r);
1459 goto err_drop;
1460 }
1461
1462 /* Freeq pointers are one page off */
1463 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1464 if (!gpage) {
1465 dev_err(geth->dev, "could not find mapping\n");
1466 continue;
1467 }
1468 page = gpage->page;
1469
1470 if (word3.bits32 & SOF_BIT) {
1471 if (skb) {
1472 napi_free_frags(&port->napi);
1473 port->stats.rx_dropped++;
1474 }
1475
1476 skb = gmac_skb_if_good_frame(port, word0, frame_len);
1477 if (!skb)
1478 goto err_drop;
1479
1480 page_offs += NET_IP_ALIGN;
1481 frag_len -= NET_IP_ALIGN;
1482 frag_nr = 0;
1483
1484 } else if (!skb) {
1485 put_page(page);
1486 continue;
1487 }
1488
1489 if (word3.bits32 & EOF_BIT)
1490 frag_len = frame_len - skb->len;
1491
1492 /* append page frag to skb */
1493 if (frag_nr == MAX_SKB_FRAGS)
1494 goto err_drop;
1495
1496 if (frag_len == 0)
1497 netdev_err(netdev, "Received fragment with len = 0\n");
1498
1499 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1500 skb->len += frag_len;
1501 skb->data_len += frag_len;
1502 skb->truesize += frag_len;
1503 frag_nr++;
1504
1505 if (word3.bits32 & EOF_BIT) {
1506 napi_gro_frags(&port->napi);
1507 skb = NULL;
1508 --budget;
1509 }
1510 continue;
1511
1512 err_drop:
1513 if (skb) {
1514 napi_free_frags(&port->napi);
1515 skb = NULL;
1516 }
1517
1518 if (mapping)
1519 put_page(page);
1520
1521 port->stats.rx_dropped++;
1522 }
1523
1524 writew(r, ptr_reg);
1525 return budget;
1526 }
1527
gmac_napi_poll(struct napi_struct *napi, int budget)1528 static int gmac_napi_poll(struct napi_struct *napi, int budget)
1529 {
1530 struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1531 struct gemini_ethernet *geth = port->geth;
1532 unsigned int freeq_threshold;
1533 unsigned int received;
1534
1535 freeq_threshold = 1 << (geth->freeq_order - 1);
1536 u64_stats_update_begin(&port->rx_stats_syncp);
1537
1538 received = gmac_rx(napi->dev, budget);
1539 if (received < budget) {
1540 napi_gro_flush(napi, false);
1541 napi_complete_done(napi, received);
1542 gmac_enable_rx_irq(napi->dev, 1);
1543 ++port->rx_napi_exits;
1544 }
1545
1546 port->freeq_refill += (budget - received);
1547 if (port->freeq_refill > freeq_threshold) {
1548 port->freeq_refill -= freeq_threshold;
1549 geth_fill_freeq(geth, true);
1550 }
1551
1552 u64_stats_update_end(&port->rx_stats_syncp);
1553 return received;
1554 }
1555
gmac_dump_dma_state(struct net_device *netdev)1556 static void gmac_dump_dma_state(struct net_device *netdev)
1557 {
1558 struct gemini_ethernet_port *port = netdev_priv(netdev);
1559 struct gemini_ethernet *geth = port->geth;
1560 void __iomem *ptr_reg;
1561 u32 reg[5];
1562
1563 /* Interrupt status */
1564 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1565 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1566 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1567 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1568 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1569 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1570 reg[0], reg[1], reg[2], reg[3], reg[4]);
1571
1572 /* Interrupt enable */
1573 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1574 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1575 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1576 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1577 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1578 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1579 reg[0], reg[1], reg[2], reg[3], reg[4]);
1580
1581 /* RX DMA status */
1582 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1583 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1584 reg[2] = GET_RPTR(port->rxq_rwptr);
1585 reg[3] = GET_WPTR(port->rxq_rwptr);
1586 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1587 reg[0], reg[1], reg[2], reg[3]);
1588
1589 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1590 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1591 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1592 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1593 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1594 reg[0], reg[1], reg[2], reg[3]);
1595
1596 /* TX DMA status */
1597 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1598
1599 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1600 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1601 reg[2] = GET_RPTR(ptr_reg);
1602 reg[3] = GET_WPTR(ptr_reg);
1603 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1604 reg[0], reg[1], reg[2], reg[3]);
1605
1606 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1607 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1608 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1609 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1610 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1611 reg[0], reg[1], reg[2], reg[3]);
1612
1613 /* FREE queues status */
1614 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1615
1616 reg[0] = GET_RPTR(ptr_reg);
1617 reg[1] = GET_WPTR(ptr_reg);
1618
1619 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1620
1621 reg[2] = GET_RPTR(ptr_reg);
1622 reg[3] = GET_WPTR(ptr_reg);
1623 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1624 reg[0], reg[1], reg[2], reg[3]);
1625 }
1626
gmac_update_hw_stats(struct net_device *netdev)1627 static void gmac_update_hw_stats(struct net_device *netdev)
1628 {
1629 struct gemini_ethernet_port *port = netdev_priv(netdev);
1630 unsigned int rx_discards, rx_mcast, rx_bcast;
1631 struct gemini_ethernet *geth = port->geth;
1632 unsigned long flags;
1633
1634 spin_lock_irqsave(&geth->irq_lock, flags);
1635 u64_stats_update_begin(&port->ir_stats_syncp);
1636
1637 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1638 port->hw_stats[0] += rx_discards;
1639 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1640 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1641 port->hw_stats[2] += rx_mcast;
1642 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1643 port->hw_stats[3] += rx_bcast;
1644 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1645 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1646
1647 port->stats.rx_missed_errors += rx_discards;
1648 port->stats.multicast += rx_mcast;
1649 port->stats.multicast += rx_bcast;
1650
1651 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1652 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1653
1654 u64_stats_update_end(&port->ir_stats_syncp);
1655 spin_unlock_irqrestore(&geth->irq_lock, flags);
1656 }
1657
1658 /**
1659 * gmac_get_intr_flags() - get interrupt status flags for a port from
1660 * @netdev: the net device for the port to get flags from
1661 * @i: the interrupt status register 0..4
1662 */
gmac_get_intr_flags(struct net_device *netdev, int i)1663 static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1664 {
1665 struct gemini_ethernet_port *port = netdev_priv(netdev);
1666 struct gemini_ethernet *geth = port->geth;
1667 void __iomem *irqif_reg, *irqen_reg;
1668 unsigned int offs, val;
1669
1670 /* Calculate the offset using the stride of the status registers */
1671 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1672 GLOBAL_INTERRUPT_STATUS_0_REG);
1673
1674 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1675 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1676
1677 val = readl(irqif_reg) & readl(irqen_reg);
1678 return val;
1679 }
1680
gmac_coalesce_delay_expired(struct hrtimer *timer)1681 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1682 {
1683 struct gemini_ethernet_port *port =
1684 container_of(timer, struct gemini_ethernet_port,
1685 rx_coalesce_timer);
1686
1687 napi_schedule(&port->napi);
1688 return HRTIMER_NORESTART;
1689 }
1690
gmac_irq(int irq, void *data)1691 static irqreturn_t gmac_irq(int irq, void *data)
1692 {
1693 struct gemini_ethernet_port *port;
1694 struct net_device *netdev = data;
1695 struct gemini_ethernet *geth;
1696 u32 val, orr = 0;
1697
1698 port = netdev_priv(netdev);
1699 geth = port->geth;
1700
1701 val = gmac_get_intr_flags(netdev, 0);
1702 orr |= val;
1703
1704 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1705 /* Oh, crap */
1706 netdev_err(netdev, "hw failure/sw bug\n");
1707 gmac_dump_dma_state(netdev);
1708
1709 /* don't know how to recover, just reduce losses */
1710 gmac_enable_irq(netdev, 0);
1711 return IRQ_HANDLED;
1712 }
1713
1714 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1715 gmac_tx_irq(netdev, 0);
1716
1717 val = gmac_get_intr_flags(netdev, 1);
1718 orr |= val;
1719
1720 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1721 gmac_enable_rx_irq(netdev, 0);
1722
1723 if (!port->rx_coalesce_nsecs) {
1724 napi_schedule(&port->napi);
1725 } else {
1726 ktime_t ktime;
1727
1728 ktime = ktime_set(0, port->rx_coalesce_nsecs);
1729 hrtimer_start(&port->rx_coalesce_timer, ktime,
1730 HRTIMER_MODE_REL);
1731 }
1732 }
1733
1734 val = gmac_get_intr_flags(netdev, 4);
1735 orr |= val;
1736
1737 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1738 gmac_update_hw_stats(netdev);
1739
1740 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1741 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1742 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1743
1744 spin_lock(&geth->irq_lock);
1745 u64_stats_update_begin(&port->ir_stats_syncp);
1746 ++port->stats.rx_fifo_errors;
1747 u64_stats_update_end(&port->ir_stats_syncp);
1748 spin_unlock(&geth->irq_lock);
1749 }
1750
1751 return orr ? IRQ_HANDLED : IRQ_NONE;
1752 }
1753
gmac_start_dma(struct gemini_ethernet_port *port)1754 static void gmac_start_dma(struct gemini_ethernet_port *port)
1755 {
1756 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1757 union gmac_dma_ctrl dma_ctrl;
1758
1759 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1760 dma_ctrl.bits.rd_enable = 1;
1761 dma_ctrl.bits.td_enable = 1;
1762 dma_ctrl.bits.loopback = 0;
1763 dma_ctrl.bits.drop_small_ack = 0;
1764 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1765 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1766 dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1767 dma_ctrl.bits.rd_bus = HSIZE_8;
1768 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1769 dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1770 dma_ctrl.bits.td_bus = HSIZE_8;
1771
1772 writel(dma_ctrl.bits32, dma_ctrl_reg);
1773 }
1774
gmac_stop_dma(struct gemini_ethernet_port *port)1775 static void gmac_stop_dma(struct gemini_ethernet_port *port)
1776 {
1777 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1778 union gmac_dma_ctrl dma_ctrl;
1779
1780 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1781 dma_ctrl.bits.rd_enable = 0;
1782 dma_ctrl.bits.td_enable = 0;
1783 writel(dma_ctrl.bits32, dma_ctrl_reg);
1784 }
1785
gmac_open(struct net_device *netdev)1786 static int gmac_open(struct net_device *netdev)
1787 {
1788 struct gemini_ethernet_port *port = netdev_priv(netdev);
1789 int err;
1790
1791 err = request_irq(netdev->irq, gmac_irq,
1792 IRQF_SHARED, netdev->name, netdev);
1793 if (err) {
1794 netdev_err(netdev, "no IRQ\n");
1795 return err;
1796 }
1797
1798 netif_carrier_off(netdev);
1799 phy_start(netdev->phydev);
1800
1801 err = geth_resize_freeq(port);
1802 /* It's fine if it's just busy, the other port has set up
1803 * the freeq in that case.
1804 */
1805 if (err && (err != -EBUSY)) {
1806 netdev_err(netdev, "could not resize freeq\n");
1807 goto err_stop_phy;
1808 }
1809
1810 err = gmac_setup_rxq(netdev);
1811 if (err) {
1812 netdev_err(netdev, "could not setup RXQ\n");
1813 goto err_stop_phy;
1814 }
1815
1816 err = gmac_setup_txqs(netdev);
1817 if (err) {
1818 netdev_err(netdev, "could not setup TXQs\n");
1819 gmac_cleanup_rxq(netdev);
1820 goto err_stop_phy;
1821 }
1822
1823 napi_enable(&port->napi);
1824
1825 gmac_start_dma(port);
1826 gmac_enable_irq(netdev, 1);
1827 gmac_enable_tx_rx(netdev);
1828 netif_tx_start_all_queues(netdev);
1829
1830 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1831 HRTIMER_MODE_REL);
1832 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1833
1834 netdev_dbg(netdev, "opened\n");
1835
1836 return 0;
1837
1838 err_stop_phy:
1839 phy_stop(netdev->phydev);
1840 free_irq(netdev->irq, netdev);
1841 return err;
1842 }
1843
gmac_stop(struct net_device *netdev)1844 static int gmac_stop(struct net_device *netdev)
1845 {
1846 struct gemini_ethernet_port *port = netdev_priv(netdev);
1847
1848 hrtimer_cancel(&port->rx_coalesce_timer);
1849 netif_tx_stop_all_queues(netdev);
1850 gmac_disable_tx_rx(netdev);
1851 gmac_stop_dma(port);
1852 napi_disable(&port->napi);
1853
1854 gmac_enable_irq(netdev, 0);
1855 gmac_cleanup_rxq(netdev);
1856 gmac_cleanup_txqs(netdev);
1857
1858 phy_stop(netdev->phydev);
1859 free_irq(netdev->irq, netdev);
1860
1861 gmac_update_hw_stats(netdev);
1862 return 0;
1863 }
1864
gmac_set_rx_mode(struct net_device *netdev)1865 static void gmac_set_rx_mode(struct net_device *netdev)
1866 {
1867 struct gemini_ethernet_port *port = netdev_priv(netdev);
1868 union gmac_rx_fltr filter = { .bits = {
1869 .broadcast = 1,
1870 .multicast = 1,
1871 .unicast = 1,
1872 } };
1873 struct netdev_hw_addr *ha;
1874 unsigned int bit_nr;
1875 u32 mc_filter[2];
1876
1877 mc_filter[1] = 0;
1878 mc_filter[0] = 0;
1879
1880 if (netdev->flags & IFF_PROMISC) {
1881 filter.bits.error = 1;
1882 filter.bits.promiscuous = 1;
1883 mc_filter[1] = ~0;
1884 mc_filter[0] = ~0;
1885 } else if (netdev->flags & IFF_ALLMULTI) {
1886 mc_filter[1] = ~0;
1887 mc_filter[0] = ~0;
1888 } else {
1889 netdev_for_each_mc_addr(ha, netdev) {
1890 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1891 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1892 }
1893 }
1894
1895 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1896 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1897 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1898 }
1899
gmac_write_mac_address(struct net_device *netdev)1900 static void gmac_write_mac_address(struct net_device *netdev)
1901 {
1902 struct gemini_ethernet_port *port = netdev_priv(netdev);
1903 __le32 addr[3];
1904
1905 memset(addr, 0, sizeof(addr));
1906 memcpy(addr, netdev->dev_addr, ETH_ALEN);
1907
1908 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1909 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1910 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1911 }
1912
gmac_set_mac_address(struct net_device *netdev, void *addr)1913 static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1914 {
1915 struct sockaddr *sa = addr;
1916
1917 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
1918 gmac_write_mac_address(netdev);
1919
1920 return 0;
1921 }
1922
gmac_clear_hw_stats(struct net_device *netdev)1923 static void gmac_clear_hw_stats(struct net_device *netdev)
1924 {
1925 struct gemini_ethernet_port *port = netdev_priv(netdev);
1926
1927 readl(port->gmac_base + GMAC_IN_DISCARDS);
1928 readl(port->gmac_base + GMAC_IN_ERRORS);
1929 readl(port->gmac_base + GMAC_IN_MCAST);
1930 readl(port->gmac_base + GMAC_IN_BCAST);
1931 readl(port->gmac_base + GMAC_IN_MAC1);
1932 readl(port->gmac_base + GMAC_IN_MAC2);
1933 }
1934
gmac_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)1935 static void gmac_get_stats64(struct net_device *netdev,
1936 struct rtnl_link_stats64 *stats)
1937 {
1938 struct gemini_ethernet_port *port = netdev_priv(netdev);
1939 unsigned int start;
1940
1941 gmac_update_hw_stats(netdev);
1942
1943 /* Racing with RX NAPI */
1944 do {
1945 start = u64_stats_fetch_begin_irq(&port->rx_stats_syncp);
1946
1947 stats->rx_packets = port->stats.rx_packets;
1948 stats->rx_bytes = port->stats.rx_bytes;
1949 stats->rx_errors = port->stats.rx_errors;
1950 stats->rx_dropped = port->stats.rx_dropped;
1951
1952 stats->rx_length_errors = port->stats.rx_length_errors;
1953 stats->rx_over_errors = port->stats.rx_over_errors;
1954 stats->rx_crc_errors = port->stats.rx_crc_errors;
1955 stats->rx_frame_errors = port->stats.rx_frame_errors;
1956
1957 } while (u64_stats_fetch_retry_irq(&port->rx_stats_syncp, start));
1958
1959 /* Racing with MIB and TX completion interrupts */
1960 do {
1961 start = u64_stats_fetch_begin_irq(&port->ir_stats_syncp);
1962
1963 stats->tx_errors = port->stats.tx_errors;
1964 stats->tx_packets = port->stats.tx_packets;
1965 stats->tx_bytes = port->stats.tx_bytes;
1966
1967 stats->multicast = port->stats.multicast;
1968 stats->rx_missed_errors = port->stats.rx_missed_errors;
1969 stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1970
1971 } while (u64_stats_fetch_retry_irq(&port->ir_stats_syncp, start));
1972
1973 /* Racing with hard_start_xmit */
1974 do {
1975 start = u64_stats_fetch_begin_irq(&port->tx_stats_syncp);
1976
1977 stats->tx_dropped = port->stats.tx_dropped;
1978
1979 } while (u64_stats_fetch_retry_irq(&port->tx_stats_syncp, start));
1980
1981 stats->rx_dropped += stats->rx_missed_errors;
1982 }
1983
gmac_change_mtu(struct net_device *netdev, int new_mtu)1984 static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1985 {
1986 int max_len = gmac_pick_rx_max_len(new_mtu);
1987
1988 if (max_len < 0)
1989 return -EINVAL;
1990
1991 gmac_disable_tx_rx(netdev);
1992
1993 netdev->mtu = new_mtu;
1994 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
1995 CONFIG0_MAXLEN_MASK);
1996
1997 netdev_update_features(netdev);
1998
1999 gmac_enable_tx_rx(netdev);
2000
2001 return 0;
2002 }
2003
gmac_set_features(struct net_device *netdev, netdev_features_t features)2004 static int gmac_set_features(struct net_device *netdev,
2005 netdev_features_t features)
2006 {
2007 struct gemini_ethernet_port *port = netdev_priv(netdev);
2008 int enable = features & NETIF_F_RXCSUM;
2009 unsigned long flags;
2010 u32 reg;
2011
2012 spin_lock_irqsave(&port->config_lock, flags);
2013
2014 reg = readl(port->gmac_base + GMAC_CONFIG0);
2015 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
2016 writel(reg, port->gmac_base + GMAC_CONFIG0);
2017
2018 spin_unlock_irqrestore(&port->config_lock, flags);
2019 return 0;
2020 }
2021
gmac_get_sset_count(struct net_device *netdev, int sset)2022 static int gmac_get_sset_count(struct net_device *netdev, int sset)
2023 {
2024 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
2025 }
2026
gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)2027 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2028 {
2029 if (stringset != ETH_SS_STATS)
2030 return;
2031
2032 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
2033 }
2034
gmac_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *estats, u64 *values)2035 static void gmac_get_ethtool_stats(struct net_device *netdev,
2036 struct ethtool_stats *estats, u64 *values)
2037 {
2038 struct gemini_ethernet_port *port = netdev_priv(netdev);
2039 unsigned int start;
2040 u64 *p;
2041 int i;
2042
2043 gmac_update_hw_stats(netdev);
2044
2045 /* Racing with MIB interrupt */
2046 do {
2047 p = values;
2048 start = u64_stats_fetch_begin_irq(&port->ir_stats_syncp);
2049
2050 for (i = 0; i < RX_STATS_NUM; i++)
2051 *p++ = port->hw_stats[i];
2052
2053 } while (u64_stats_fetch_retry_irq(&port->ir_stats_syncp, start));
2054 values = p;
2055
2056 /* Racing with RX NAPI */
2057 do {
2058 p = values;
2059 start = u64_stats_fetch_begin_irq(&port->rx_stats_syncp);
2060
2061 for (i = 0; i < RX_STATUS_NUM; i++)
2062 *p++ = port->rx_stats[i];
2063 for (i = 0; i < RX_CHKSUM_NUM; i++)
2064 *p++ = port->rx_csum_stats[i];
2065 *p++ = port->rx_napi_exits;
2066
2067 } while (u64_stats_fetch_retry_irq(&port->rx_stats_syncp, start));
2068 values = p;
2069
2070 /* Racing with TX start_xmit */
2071 do {
2072 p = values;
2073 start = u64_stats_fetch_begin_irq(&port->tx_stats_syncp);
2074
2075 for (i = 0; i < TX_MAX_FRAGS; i++) {
2076 *values++ = port->tx_frag_stats[i];
2077 port->tx_frag_stats[i] = 0;
2078 }
2079 *values++ = port->tx_frags_linearized;
2080 *values++ = port->tx_hw_csummed;
2081
2082 } while (u64_stats_fetch_retry_irq(&port->tx_stats_syncp, start));
2083 }
2084
gmac_get_ksettings(struct net_device *netdev, struct ethtool_link_ksettings *cmd)2085 static int gmac_get_ksettings(struct net_device *netdev,
2086 struct ethtool_link_ksettings *cmd)
2087 {
2088 if (!netdev->phydev)
2089 return -ENXIO;
2090 phy_ethtool_ksettings_get(netdev->phydev, cmd);
2091
2092 return 0;
2093 }
2094
gmac_set_ksettings(struct net_device *netdev, const struct ethtool_link_ksettings *cmd)2095 static int gmac_set_ksettings(struct net_device *netdev,
2096 const struct ethtool_link_ksettings *cmd)
2097 {
2098 if (!netdev->phydev)
2099 return -ENXIO;
2100 return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2101 }
2102
gmac_nway_reset(struct net_device *netdev)2103 static int gmac_nway_reset(struct net_device *netdev)
2104 {
2105 if (!netdev->phydev)
2106 return -ENXIO;
2107 return phy_start_aneg(netdev->phydev);
2108 }
2109
gmac_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pparam)2110 static void gmac_get_pauseparam(struct net_device *netdev,
2111 struct ethtool_pauseparam *pparam)
2112 {
2113 struct gemini_ethernet_port *port = netdev_priv(netdev);
2114 union gmac_config0 config0;
2115
2116 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2117
2118 pparam->rx_pause = config0.bits.rx_fc_en;
2119 pparam->tx_pause = config0.bits.tx_fc_en;
2120 pparam->autoneg = true;
2121 }
2122
gmac_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *rp)2123 static void gmac_get_ringparam(struct net_device *netdev,
2124 struct ethtool_ringparam *rp)
2125 {
2126 struct gemini_ethernet_port *port = netdev_priv(netdev);
2127
2128 readl(port->gmac_base + GMAC_CONFIG0);
2129
2130 rp->rx_max_pending = 1 << 15;
2131 rp->rx_mini_max_pending = 0;
2132 rp->rx_jumbo_max_pending = 0;
2133 rp->tx_max_pending = 1 << 15;
2134
2135 rp->rx_pending = 1 << port->rxq_order;
2136 rp->rx_mini_pending = 0;
2137 rp->rx_jumbo_pending = 0;
2138 rp->tx_pending = 1 << port->txq_order;
2139 }
2140
gmac_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *rp)2141 static int gmac_set_ringparam(struct net_device *netdev,
2142 struct ethtool_ringparam *rp)
2143 {
2144 struct gemini_ethernet_port *port = netdev_priv(netdev);
2145 int err = 0;
2146
2147 if (netif_running(netdev))
2148 return -EBUSY;
2149
2150 if (rp->rx_pending) {
2151 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2152 err = geth_resize_freeq(port);
2153 }
2154 if (rp->tx_pending) {
2155 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2156 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2157 }
2158
2159 return err;
2160 }
2161
gmac_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)2162 static int gmac_get_coalesce(struct net_device *netdev,
2163 struct ethtool_coalesce *ecmd)
2164 {
2165 struct gemini_ethernet_port *port = netdev_priv(netdev);
2166
2167 ecmd->rx_max_coalesced_frames = 1;
2168 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2169 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2170
2171 return 0;
2172 }
2173
gmac_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)2174 static int gmac_set_coalesce(struct net_device *netdev,
2175 struct ethtool_coalesce *ecmd)
2176 {
2177 struct gemini_ethernet_port *port = netdev_priv(netdev);
2178
2179 if (ecmd->tx_max_coalesced_frames < 1)
2180 return -EINVAL;
2181 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2182 return -EINVAL;
2183
2184 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2185 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2186
2187 return 0;
2188 }
2189
gmac_get_msglevel(struct net_device *netdev)2190 static u32 gmac_get_msglevel(struct net_device *netdev)
2191 {
2192 struct gemini_ethernet_port *port = netdev_priv(netdev);
2193
2194 return port->msg_enable;
2195 }
2196
gmac_set_msglevel(struct net_device *netdev, u32 level)2197 static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2198 {
2199 struct gemini_ethernet_port *port = netdev_priv(netdev);
2200
2201 port->msg_enable = level;
2202 }
2203
gmac_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)2204 static void gmac_get_drvinfo(struct net_device *netdev,
2205 struct ethtool_drvinfo *info)
2206 {
2207 strcpy(info->driver, DRV_NAME);
2208 strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2209 }
2210
2211 static const struct net_device_ops gmac_351x_ops = {
2212 .ndo_init = gmac_init,
2213 .ndo_open = gmac_open,
2214 .ndo_stop = gmac_stop,
2215 .ndo_start_xmit = gmac_start_xmit,
2216 .ndo_tx_timeout = gmac_tx_timeout,
2217 .ndo_set_rx_mode = gmac_set_rx_mode,
2218 .ndo_set_mac_address = gmac_set_mac_address,
2219 .ndo_get_stats64 = gmac_get_stats64,
2220 .ndo_change_mtu = gmac_change_mtu,
2221 .ndo_set_features = gmac_set_features,
2222 };
2223
2224 static const struct ethtool_ops gmac_351x_ethtool_ops = {
2225 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
2226 ETHTOOL_COALESCE_MAX_FRAMES,
2227 .get_sset_count = gmac_get_sset_count,
2228 .get_strings = gmac_get_strings,
2229 .get_ethtool_stats = gmac_get_ethtool_stats,
2230 .get_link = ethtool_op_get_link,
2231 .get_link_ksettings = gmac_get_ksettings,
2232 .set_link_ksettings = gmac_set_ksettings,
2233 .nway_reset = gmac_nway_reset,
2234 .get_pauseparam = gmac_get_pauseparam,
2235 .get_ringparam = gmac_get_ringparam,
2236 .set_ringparam = gmac_set_ringparam,
2237 .get_coalesce = gmac_get_coalesce,
2238 .set_coalesce = gmac_set_coalesce,
2239 .get_msglevel = gmac_get_msglevel,
2240 .set_msglevel = gmac_set_msglevel,
2241 .get_drvinfo = gmac_get_drvinfo,
2242 };
2243
gemini_port_irq_thread(int irq, void *data)2244 static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2245 {
2246 unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2247 struct gemini_ethernet_port *port = data;
2248 struct gemini_ethernet *geth;
2249 unsigned long flags;
2250
2251 geth = port->geth;
2252 /* The queue is half empty so refill it */
2253 geth_fill_freeq(geth, true);
2254
2255 spin_lock_irqsave(&geth->irq_lock, flags);
2256 /* ACK queue interrupt */
2257 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2258 /* Enable queue interrupt again */
2259 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2260 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2261 spin_unlock_irqrestore(&geth->irq_lock, flags);
2262
2263 return IRQ_HANDLED;
2264 }
2265
gemini_port_irq(int irq, void *data)2266 static irqreturn_t gemini_port_irq(int irq, void *data)
2267 {
2268 struct gemini_ethernet_port *port = data;
2269 struct gemini_ethernet *geth;
2270 irqreturn_t ret = IRQ_NONE;
2271 u32 val, en;
2272
2273 geth = port->geth;
2274 spin_lock(&geth->irq_lock);
2275
2276 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2277 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2278
2279 if (val & en & SWFQ_EMPTY_INT_BIT) {
2280 /* Disable the queue empty interrupt while we work on
2281 * processing the queue. Also disable overrun interrupts
2282 * as there is not much we can do about it here.
2283 */
2284 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2285 | GMAC1_RX_OVERRUN_INT_BIT);
2286 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2287 ret = IRQ_WAKE_THREAD;
2288 }
2289
2290 spin_unlock(&geth->irq_lock);
2291
2292 return ret;
2293 }
2294
gemini_port_remove(struct gemini_ethernet_port *port)2295 static void gemini_port_remove(struct gemini_ethernet_port *port)
2296 {
2297 if (port->netdev) {
2298 phy_disconnect(port->netdev->phydev);
2299 unregister_netdev(port->netdev);
2300 }
2301 clk_disable_unprepare(port->pclk);
2302 geth_cleanup_freeq(port->geth);
2303 }
2304
gemini_ethernet_init(struct gemini_ethernet *geth)2305 static void gemini_ethernet_init(struct gemini_ethernet *geth)
2306 {
2307 /* Only do this once both ports are online */
2308 if (geth->initialized)
2309 return;
2310 if (geth->port0 && geth->port1)
2311 geth->initialized = true;
2312 else
2313 return;
2314
2315 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2316 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2317 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2318 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2319 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2320
2321 /* Interrupt config:
2322 *
2323 * GMAC0 intr bits ------> int0 ----> eth0
2324 * GMAC1 intr bits ------> int1 ----> eth1
2325 * TOE intr -------------> int1 ----> eth1
2326 * Classification Intr --> int0 ----> eth0
2327 * Default Q0 -----------> int0 ----> eth0
2328 * Default Q1 -----------> int1 ----> eth1
2329 * FreeQ intr -----------> int1 ----> eth1
2330 */
2331 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2332 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2333 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2334 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2335 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2336
2337 /* edge-triggered interrupts packed to level-triggered one... */
2338 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2339 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2340 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2341 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2342 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2343
2344 /* Set up queue */
2345 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2346 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2347 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2348 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2349
2350 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2351 /* This makes the queue resize on probe() so that we
2352 * set up and enable the queue IRQ. FIXME: fragile.
2353 */
2354 geth->freeq_order = 1;
2355 }
2356
gemini_port_save_mac_addr(struct gemini_ethernet_port *port)2357 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2358 {
2359 port->mac_addr[0] =
2360 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2361 port->mac_addr[1] =
2362 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2363 port->mac_addr[2] =
2364 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2365 }
2366
gemini_ethernet_port_probe(struct platform_device *pdev)2367 static int gemini_ethernet_port_probe(struct platform_device *pdev)
2368 {
2369 char *port_names[2] = { "ethernet0", "ethernet1" };
2370 struct gemini_ethernet_port *port;
2371 struct device *dev = &pdev->dev;
2372 struct gemini_ethernet *geth;
2373 struct net_device *netdev;
2374 struct resource *gmacres;
2375 struct resource *dmares;
2376 struct device *parent;
2377 unsigned int id;
2378 int irq;
2379 int ret;
2380
2381 parent = dev->parent;
2382 geth = dev_get_drvdata(parent);
2383
2384 if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2385 id = 0;
2386 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2387 id = 1;
2388 else
2389 return -ENODEV;
2390
2391 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2392
2393 netdev = devm_alloc_etherdev_mqs(dev, sizeof(*port), TX_QUEUE_NUM, TX_QUEUE_NUM);
2394 if (!netdev) {
2395 dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2396 return -ENOMEM;
2397 }
2398
2399 port = netdev_priv(netdev);
2400 SET_NETDEV_DEV(netdev, dev);
2401 port->netdev = netdev;
2402 port->id = id;
2403 port->geth = geth;
2404 port->dev = dev;
2405 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2406
2407 /* DMA memory */
2408 dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2409 if (!dmares) {
2410 dev_err(dev, "no DMA resource\n");
2411 return -ENODEV;
2412 }
2413 port->dma_base = devm_ioremap_resource(dev, dmares);
2414 if (IS_ERR(port->dma_base))
2415 return PTR_ERR(port->dma_base);
2416
2417 /* GMAC config memory */
2418 gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2419 if (!gmacres) {
2420 dev_err(dev, "no GMAC resource\n");
2421 return -ENODEV;
2422 }
2423 port->gmac_base = devm_ioremap_resource(dev, gmacres);
2424 if (IS_ERR(port->gmac_base))
2425 return PTR_ERR(port->gmac_base);
2426
2427 /* Interrupt */
2428 irq = platform_get_irq(pdev, 0);
2429 if (irq <= 0)
2430 return irq ? irq : -ENODEV;
2431 port->irq = irq;
2432
2433 /* Clock the port */
2434 port->pclk = devm_clk_get(dev, "PCLK");
2435 if (IS_ERR(port->pclk)) {
2436 dev_err(dev, "no PCLK\n");
2437 return PTR_ERR(port->pclk);
2438 }
2439 ret = clk_prepare_enable(port->pclk);
2440 if (ret)
2441 return ret;
2442
2443 /* Maybe there is a nice ethernet address we should use */
2444 gemini_port_save_mac_addr(port);
2445
2446 /* Reset the port */
2447 port->reset = devm_reset_control_get_exclusive(dev, NULL);
2448 if (IS_ERR(port->reset)) {
2449 dev_err(dev, "no reset\n");
2450 ret = PTR_ERR(port->reset);
2451 goto unprepare;
2452 }
2453 reset_control_reset(port->reset);
2454 usleep_range(100, 500);
2455
2456 /* Assign pointer in the main state container */
2457 if (!id)
2458 geth->port0 = port;
2459 else
2460 geth->port1 = port;
2461
2462 /* This will just be done once both ports are up and reset */
2463 gemini_ethernet_init(geth);
2464
2465 platform_set_drvdata(pdev, port);
2466
2467 /* Set up and register the netdev */
2468 netdev->dev_id = port->id;
2469 netdev->irq = irq;
2470 netdev->netdev_ops = &gmac_351x_ops;
2471 netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2472
2473 spin_lock_init(&port->config_lock);
2474 gmac_clear_hw_stats(netdev);
2475
2476 netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2477 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2478 /* We can receive jumbo frames up to 10236 bytes but only
2479 * transmit 2047 bytes so, let's accept payloads of 2047
2480 * bytes minus VLAN and ethernet header
2481 */
2482 netdev->min_mtu = ETH_MIN_MTU;
2483 netdev->max_mtu = MTU_SIZE_BIT_MASK - VLAN_ETH_HLEN;
2484
2485 port->freeq_refill = 0;
2486 netif_napi_add(netdev, &port->napi, gmac_napi_poll,
2487 DEFAULT_NAPI_WEIGHT);
2488
2489 if (is_valid_ether_addr((void *)port->mac_addr)) {
2490 memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
2491 } else {
2492 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2493 port->mac_addr[0], port->mac_addr[1],
2494 port->mac_addr[2]);
2495 dev_info(dev, "using a random ethernet address\n");
2496 eth_random_addr(netdev->dev_addr);
2497 }
2498 gmac_write_mac_address(netdev);
2499
2500 ret = devm_request_threaded_irq(port->dev,
2501 port->irq,
2502 gemini_port_irq,
2503 gemini_port_irq_thread,
2504 IRQF_SHARED,
2505 port_names[port->id],
2506 port);
2507 if (ret)
2508 goto unprepare;
2509
2510 ret = gmac_setup_phy(netdev);
2511 if (ret) {
2512 netdev_err(netdev,
2513 "PHY init failed\n");
2514 goto unprepare;
2515 }
2516
2517 ret = register_netdev(netdev);
2518 if (ret)
2519 goto unprepare;
2520
2521 netdev_info(netdev,
2522 "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
2523 port->irq, &dmares->start,
2524 &gmacres->start);
2525 return 0;
2526
2527 unprepare:
2528 clk_disable_unprepare(port->pclk);
2529 return ret;
2530 }
2531
gemini_ethernet_port_remove(struct platform_device *pdev)2532 static int gemini_ethernet_port_remove(struct platform_device *pdev)
2533 {
2534 struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2535
2536 gemini_port_remove(port);
2537
2538 return 0;
2539 }
2540
2541 static const struct of_device_id gemini_ethernet_port_of_match[] = {
2542 {
2543 .compatible = "cortina,gemini-ethernet-port",
2544 },
2545 {},
2546 };
2547 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2548
2549 static struct platform_driver gemini_ethernet_port_driver = {
2550 .driver = {
2551 .name = "gemini-ethernet-port",
2552 .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
2553 },
2554 .probe = gemini_ethernet_port_probe,
2555 .remove = gemini_ethernet_port_remove,
2556 };
2557
gemini_ethernet_probe(struct platform_device *pdev)2558 static int gemini_ethernet_probe(struct platform_device *pdev)
2559 {
2560 struct device *dev = &pdev->dev;
2561 struct gemini_ethernet *geth;
2562 unsigned int retry = 5;
2563 struct resource *res;
2564 u32 val;
2565
2566 /* Global registers */
2567 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2568 if (!geth)
2569 return -ENOMEM;
2570 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2571 if (!res)
2572 return -ENODEV;
2573 geth->base = devm_ioremap_resource(dev, res);
2574 if (IS_ERR(geth->base))
2575 return PTR_ERR(geth->base);
2576 geth->dev = dev;
2577
2578 /* Wait for ports to stabilize */
2579 do {
2580 udelay(2);
2581 val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2582 barrier();
2583 } while (!val && --retry);
2584 if (!retry) {
2585 dev_err(dev, "failed to reset ethernet\n");
2586 return -EIO;
2587 }
2588 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2589 (val >> 4) & 0xFFFU, val & 0xFU);
2590
2591 spin_lock_init(&geth->irq_lock);
2592 spin_lock_init(&geth->freeq_lock);
2593
2594 /* The children will use this */
2595 platform_set_drvdata(pdev, geth);
2596
2597 /* Spawn child devices for the two ports */
2598 return devm_of_platform_populate(dev);
2599 }
2600
gemini_ethernet_remove(struct platform_device *pdev)2601 static int gemini_ethernet_remove(struct platform_device *pdev)
2602 {
2603 struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2604
2605 geth_cleanup_freeq(geth);
2606 geth->initialized = false;
2607
2608 return 0;
2609 }
2610
2611 static const struct of_device_id gemini_ethernet_of_match[] = {
2612 {
2613 .compatible = "cortina,gemini-ethernet",
2614 },
2615 {},
2616 };
2617 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2618
2619 static struct platform_driver gemini_ethernet_driver = {
2620 .driver = {
2621 .name = DRV_NAME,
2622 .of_match_table = of_match_ptr(gemini_ethernet_of_match),
2623 },
2624 .probe = gemini_ethernet_probe,
2625 .remove = gemini_ethernet_remove,
2626 };
2627
gemini_ethernet_module_init(void)2628 static int __init gemini_ethernet_module_init(void)
2629 {
2630 int ret;
2631
2632 ret = platform_driver_register(&gemini_ethernet_port_driver);
2633 if (ret)
2634 return ret;
2635
2636 ret = platform_driver_register(&gemini_ethernet_driver);
2637 if (ret) {
2638 platform_driver_unregister(&gemini_ethernet_port_driver);
2639 return ret;
2640 }
2641
2642 return 0;
2643 }
2644 module_init(gemini_ethernet_module_init);
2645
gemini_ethernet_module_exit(void)2646 static void __exit gemini_ethernet_module_exit(void)
2647 {
2648 platform_driver_unregister(&gemini_ethernet_driver);
2649 platform_driver_unregister(&gemini_ethernet_port_driver);
2650 }
2651 module_exit(gemini_ethernet_module_exit);
2652
2653 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2654 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2655 MODULE_LICENSE("GPL");
2656 MODULE_ALIAS("platform:" DRV_NAME);
2657