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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_nbio.c35 if (!adev->nbio.ras_if) { in amdgpu_nbio_ras_late_init()
36 adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); in amdgpu_nbio_ras_late_init()
37 if (!adev->nbio.ras_if) in amdgpu_nbio_ras_late_init()
39 adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_late_init()
40 adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_late_init()
41 adev->nbio.ras_if->sub_block_index = 0; in amdgpu_nbio_ras_late_init()
42 strcpy(adev->nbio.ras_if->name, "pcie_bif"); in amdgpu_nbio_ras_late_init()
44 ih_info.head = fs_info.head = *adev->nbio.ras_if; in amdgpu_nbio_ras_late_init()
45 r = amdgpu_ras_late_init(adev, adev->nbio.ras_if, in amdgpu_nbio_ras_late_init()
50 if (amdgpu_ras_is_supported(adev, adev->nbio in amdgpu_nbio_ras_late_init()
[all...]
H A Dsoc15.c47 #include "nbio/nbio_7_0_default.h"
48 #include "nbio/nbio_7_0_offset.h"
49 #include "nbio/nbio_7_0_sh_mask.h"
50 #include "nbio/nbio_7_0_smn.h"
105 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
106 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
115 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
116 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
124 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
125 data = adev->nbio in soc15_pcie_rreg64()
[all...]
H A Dnv.c73 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
74 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
83 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
84 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
92 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
93 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
102 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
103 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
138 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
295 u32 memsize = adev->nbio in nv_asic_mode1_reset()
[all...]
H A Ddf_v3_6.c105 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_get_fica()
106 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_get_fica()
128 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_set_fica()
129 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_set_fica()
156 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_rreg()
157 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_rreg()
178 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_wreg()
179 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_wreg()
197 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_arm_with_status()
198 data = adev->nbio in df_v3_6_perfmon_arm_with_status()
[all...]
H A Dnbio_v7_4.c28 #include "nbio/nbio_7_4_offset.h"
29 #include "nbio/nbio_7_4_sh_mask.h"
30 #include "nbio/nbio_7_4_0_smn.h"
31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
37 * These are nbio v7_4_1 registers mask. Temporarily define these here since
38 * nbio v7_4_1 header is incomplete.
303 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
333 adev->nbio.ras_if->name); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
339 adev->nbio.ras_if->name); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
457 adev->nbio in nbio_v7_4_init_ras_controller_interrupt()
[all...]
H A Damdgpu_irq.c167 if (adev->nbio.funcs && in amdgpu_irq_handler()
168 adev->nbio.funcs->handle_ras_controller_intr_no_bifring) in amdgpu_irq_handler()
169 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev); in amdgpu_irq_handler()
171 if (adev->nbio.funcs && in amdgpu_irq_handler()
172 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring) in amdgpu_irq_handler()
173 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev); in amdgpu_irq_handler()
H A Dgmc_v10_0.c283 adev->nbio.funcs->hdp_flush(adev, NULL); in gmc_v10_0_flush_gpu_tlb()
726 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v10_0_mc_init()
967 adev->nbio.funcs->hdp_flush(adev, NULL); in gmc_v10_0_gart_enable()
H A Damdgpu_ras.c35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
794 if (adev->nbio.funcs->query_ras_error_count) in amdgpu_ras_error_query()
795 adev->nbio.funcs->query_ras_error_count(adev, &err_data); in amdgpu_ras_error_query()
2064 if (adev->nbio.funcs->init_ras_controller_interrupt) { in amdgpu_ras_init()
2065 r = adev->nbio.funcs->init_ras_controller_interrupt(adev); in amdgpu_ras_init()
2070 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { in amdgpu_ras_init()
2071 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); in amdgpu_ras_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_nbio.c30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
50 if (adev->nbio.funcs && adev->nbio.funcs->get_pcie_replay_count) in amdgpu_nbio_get_pcie_replay_count()
51 return adev->nbio.funcs->get_pcie_replay_count(adev); in amdgpu_nbio_get_pcie_replay_count()
59 if (adev->nbio.funcs->get_pcie_usage) in amdgpu_nbio_get_pcie_usage()
60 adev->nbio.funcs->get_pcie_usage(adev, count0, count1); in amdgpu_nbio_get_pcie_usage()
72 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0); in amdgpu_nbio_ras_late_init()
75 r = amdgpu_irq_get(adev, &adev->nbio in amdgpu_nbio_ras_late_init()
[all...]
H A Dsoc21.c222 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
351 u32 memsize = adev->nbio.funcs->get_memsize(adev);
436 (adev->nbio.funcs->program_aspm)) in soc21_program_aspm()
437 adev->nbio.funcs->program_aspm(adev); in soc21_program_aspm()
725 if (adev->nbio.ras && in soc21_common_late_init()
726 adev->nbio.ras_err_event_athub_irq.funcs) in soc21_common_late_init()
729 * nbio v4_3 only support fatal error hanlding in soc21_common_late_init()
731 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc21_common_late_init()
737 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc21_common_late_init()
763 /* setup nbio register in soc21_common_hw_init()
[all...]
H A Dsoc15.c45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
320 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
673 (adev->nbio.funcs->program_aspm)) in soc15_program_aspm()
674 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
1215 adev->nbio in soc15_common_late_init()
[all...]
H A Dnv.c309 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
431 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
520 (adev->nbio.funcs->program_aspm)) in nv_program_aspm()
521 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
613 (adev->nbio.funcs->enable_aspm) && in nv_update_umd_stable_pstate()
615 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
978 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in nv_common_late_init()
1002 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
1003 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
1005 if (adev->nbio in nv_common_hw_init()
[all...]
H A Dnbio_v7_9.c28 #include "nbio/nbio_7_9_0_offset.h"
29 #include "nbio/nbio_7_9_0_sh_mask.h"
30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
571 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); in nbio_v7_9_handle_ras_controller_intr_no_bifring()
602 get_ras_block_str(adev->nbio.ras_if)); in nbio_v7_9_handle_ras_controller_intr_no_bifring()
608 get_ras_block_str(adev->nbio.ras_if)); in nbio_v7_9_handle_ras_controller_intr_no_bifring()
694 adev->nbio.ras_controller_irq.funcs = in nbio_v7_9_init_ras_controller_interrupt()
696 adev->nbio.ras_controller_irq.num_types = 1; in nbio_v7_9_init_ras_controller_interrupt()
701 &adev->nbio.ras_controller_irq); in nbio_v7_9_init_ras_controller_interrupt()
712 adev->nbio in nbio_v7_9_init_ras_err_event_athub_interrupt()
[all...]
H A Ddf_v3_6.c51 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_get_fica()
52 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_get_fica()
74 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_set_fica()
75 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_set_fica()
102 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_rreg()
103 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_rreg()
124 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_wreg()
125 data = adev->nbio.funcs->get_pcie_data_offset(adev); in df_v3_6_perfmon_wreg()
143 address = adev->nbio.funcs->get_pcie_index_offset(adev); in df_v3_6_perfmon_arm_with_status()
144 data = adev->nbio in df_v3_6_perfmon_arm_with_status()
[all...]
H A Dnbio_v7_4.c28 #include "nbio/nbio_7_4_offset.h"
29 #include "nbio/nbio_7_4_sh_mask.h"
30 #include "nbio/nbio_7_4_0_smn.h"
31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
56 * These are nbio v7_4_1 registers mask. Temporarily define these here since
57 * nbio v7_4_1 header is incomplete.
367 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
404 get_ras_block_str(adev->nbio.ras_if)); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
410 get_ras_block_str(adev->nbio.ras_if)); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
553 adev->nbio in nbio_v7_4_init_ras_controller_interrupt()
[all...]
H A Damdgpu_discovery.c2410 adev->nbio.funcs = &nbio_v6_1_funcs; in amdgpu_discovery_set_ip_blocks()
2411 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2416 adev->nbio.funcs = &nbio_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2417 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2422 adev->nbio.funcs = &nbio_v7_4_funcs; in amdgpu_discovery_set_ip_blocks()
2423 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2426 adev->nbio.funcs = &nbio_v7_9_funcs; in amdgpu_discovery_set_ip_blocks()
2427 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2434 adev->nbio.funcs = &nbio_v7_2_funcs; in amdgpu_discovery_set_ip_blocks()
2435 adev->nbio in amdgpu_discovery_set_ip_blocks()
[all...]
H A Damdgpu_ras.c36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
1653 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
1654 adev->nbio.ras->handle_ras_controller_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
1655 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
1657 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
1658 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
1659 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
2637 /* initialize nbio ras function ahead of any other in amdgpu_ras_init()
2645 adev->nbio.ras = &nbio_v7_4_ras; in amdgpu_ras_init()
2649 /* unlike other generation of nbio ra in amdgpu_ras_init()
[all...]
H A Damdgpu_device.c549 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg()
550 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); in amdgpu_device_indirect_rreg()
573 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg_ext()
574 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); in amdgpu_device_indirect_rreg_ext()
575 if (adev->nbio.funcs->get_pcie_index_hi_offset) in amdgpu_device_indirect_rreg_ext()
576 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); in amdgpu_device_indirect_rreg_ext()
622 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg64()
623 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); in amdgpu_device_indirect_rreg64()
657 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_wreg()
658 pcie_data = adev->nbio in amdgpu_device_indirect_wreg()
[all...]
H A Damdgpu_bios.c502 if (adev->nbio.funcs && in amdgpu_soc15_read_bios_from_rom()
503 adev->nbio.funcs->get_rom_offset) { in amdgpu_soc15_read_bios_from_rom()
504 rom_offset = adev->nbio.funcs->get_rom_offset(adev); in amdgpu_soc15_read_bios_from_rom()
H A Dnbio_v4_3.c27 #include "nbio/nbio_4_3_0_offset.h"
28 #include "nbio/nbio_4_3_0_sh_mask.h"
29 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
606 adev->nbio.ras_err_event_athub_irq.funcs = in nbio_v4_3_init_ras_err_event_athub_interrupt()
608 adev->nbio.ras_err_event_athub_irq.num_types = 1; in nbio_v4_3_init_ras_err_event_athub_interrupt()
611 * nbio v4_3 uses the same irq source as nbio v7_4 */ in nbio_v4_3_init_ras_err_event_athub_interrupt()
614 &adev->nbio.ras_err_event_athub_irq); in nbio_v4_3_init_ras_err_event_athub_interrupt()
H A Dvega10_ih.c273 adev->nbio.funcs->ih_control(adev); in vega10_ih_irq_init()
293 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega10_ih_irq_init()
H A Daqua_vanjaram.c304 if (adev->nbio.funcs->get_compute_partition_mode) in aqua_vanjaram_query_partition_mode()
305 mode = adev->nbio.funcs->get_compute_partition_mode(adev); in aqua_vanjaram_query_partition_mode()
H A Dih_v6_0.c306 adev->nbio.funcs->ih_control(adev); in ih_v6_0_irq_init()
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_0_irq_init()
H A Dih_v6_1.c306 adev->nbio.funcs->ih_control(adev); in ih_v6_1_irq_init()
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_1_irq_init()
/kernel/linux/linux-5.10/drivers/block/xen-blkback/
H A Dblkback.c1194 int i, nbio = 0; in dispatch_rw_block_io() local
1335 biolist[nbio++] = bio; in dispatch_rw_block_io()
1354 biolist[nbio++] = bio; in dispatch_rw_block_io()
1361 atomic_set(&pending_req->pendcnt, nbio); in dispatch_rw_block_io()
1364 for (i = 0; i < nbio; i++) in dispatch_rw_block_io()
1388 for (i = 0; i < nbio; i++) in dispatch_rw_block_io()

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