Lines Matching refs:nbio
47 #include "nbio/nbio_7_0_default.h"
48 #include "nbio/nbio_7_0_offset.h"
49 #include "nbio/nbio_7_0_sh_mask.h"
50 #include "nbio/nbio_7_0_smn.h"
105 address = adev->nbio.funcs->get_pcie_index_offset(adev);
106 data = adev->nbio.funcs->get_pcie_data_offset(adev);
115 address = adev->nbio.funcs->get_pcie_index_offset(adev);
116 data = adev->nbio.funcs->get_pcie_data_offset(adev);
124 address = adev->nbio.funcs->get_pcie_index_offset(adev);
125 data = adev->nbio.funcs->get_pcie_data_offset(adev);
134 address = adev->nbio.funcs->get_pcie_index_offset(adev);
135 data = adev->nbio.funcs->get_pcie_data_offset(adev);
242 return adev->nbio.funcs->get_memsize(adev);
465 u32 memsize = adev->nbio.funcs->get_memsize(adev);
484 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
492 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
634 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
635 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
649 return adev->nbio.funcs->get_rev_id(adev);
707 adev->nbio.funcs = &nbio_v7_0_funcs;
708 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
711 adev->nbio.funcs = &nbio_v7_4_funcs;
712 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
714 adev->nbio.funcs = &nbio_v6_1_funcs;
715 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
842 adev->nbio.funcs->hdp_flush(adev, ring);
1309 if (adev->nbio.funcs->ras_late_init)
1310 r = adev->nbio.funcs->ras_late_init(adev);
1345 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1350 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1363 /* setup nbio registers */
1364 adev->nbio.funcs->init_registers(adev);
1369 if (adev->nbio.funcs->remap_hdp_registers)
1370 adev->nbio.funcs->remap_hdp_registers(adev);
1393 if (adev->nbio.ras_if &&
1394 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1395 if (adev->nbio.funcs->init_ras_controller_interrupt)
1396 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1397 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1398 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1542 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1544 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1559 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1561 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1590 adev->nbio.funcs->get_clockgating_state(adev, flags);