Lines Matching refs:nbio
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
320 return adev->nbio.funcs->get_memsize(adev);
489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
673 (adev->nbio.funcs->program_aspm))
674 adev->nbio.funcs->program_aspm(adev);
1215 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1251 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1264 /* setup nbio registers */
1265 adev->nbio.funcs->init_registers(adev);
1270 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1271 adev->nbio.funcs->remap_hdp_registers(adev);
1274 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1296 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1297 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1302 if (adev->nbio.ras_if &&
1303 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1304 if (adev->nbio.ras &&
1305 adev->nbio.ras->init_ras_controller_interrupt)
1306 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1307 if (adev->nbio.ras &&
1308 adev->nbio.ras->init_ras_err_event_athub_interrupt)
1309 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1404 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1406 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1422 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1424 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1452 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1453 adev->nbio.funcs->get_clockgating_state(adev, flags);