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/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk.c21 unit->clk_data.clks = clk_table; in mmp_clk_init()
27 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks()
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
49 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks()
26 mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_rate_clk *clks, int size) mmp_register_fixed_rate_clks() argument
48 mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_factor_clk *clks, int size) mmp_register_fixed_factor_clks() argument
70 mmp_register_general_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_general_gate_clk *clks, void __iomem *base, int size) mmp_register_general_gate_clks() argument
96 mmp_register_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_gate_clk *clks, void __iomem *base, int size) mmp_register_gate_clks() argument
124 mmp_register_mux_clks(struct mmp_clk_unit *unit, struct mmp_param_mux_clk *clks, void __iomem *base, int size) mmp_register_mux_clks() argument
152 mmp_register_div_clks(struct mmp_clk_unit *unit, struct mmp_param_div_clk *clks, void __iomem *base, int size) mmp_register_div_clks() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/mmp/
H A Dclk.c21 unit->clk_data.clks = clk_table; in mmp_clk_init()
27 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks()
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
49 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks()
26 mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_rate_clk *clks, int size) mmp_register_fixed_rate_clks() argument
48 mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_factor_clk *clks, int size) mmp_register_fixed_factor_clks() argument
70 mmp_register_general_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_general_gate_clk *clks, void __iomem *base, int size) mmp_register_general_gate_clks() argument
96 mmp_register_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_gate_clk *clks, void __iomem *base, int size) mmp_register_gate_clks() argument
124 mmp_register_mux_clks(struct mmp_clk_unit *unit, struct mmp_param_mux_clk *clks, void __iomem *base, int size) mmp_register_mux_clks() argument
152 mmp_register_div_clks(struct mmp_clk_unit *unit, struct mmp_param_div_clk *clks, void __iomem *base, int size) mmp_register_div_clks() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx8qxp.c24 struct clk_hw **clks; in imx8qxp_clk_probe() local
37 clks = clk_data->hws; in imx8qxp_clk_probe()
40 clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0); in imx8qxp_clk_probe()
41 clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000); in imx8qxp_clk_probe()
42 clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333); in imx8qxp_clk_probe()
43 clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666); in imx8qxp_clk_probe()
44 clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333); in imx8qxp_clk_probe()
45 clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000); in imx8qxp_clk_probe()
46 clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000); in imx8qxp_clk_probe()
47 clks[IMX_DC_CFG_CL in imx8qxp_clk_probe()
[all...]
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx8ulp.c149 struct clk_hw **clks; in imx8ulp_clk_cgc1_init() local
158 clks = clk_data->hws; in imx8ulp_clk_cgc1_init()
160 clks[IMX8ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8ulp_clk_cgc1_init()
167 clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc1_init()
168 clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx8ulp_clk_cgc1_init()
170 clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500); in imx8ulp_clk_cgc1_init()
171 clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600); in imx8ulp_clk_cgc1_init()
172 clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6); in imx8ulp_clk_cgc1_init()
174 clks[IMX8ULP_CLK_SPLL3_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd0", "spll3_vcodiv", base + 0x614, 0); in imx8ulp_clk_cgc1_init()
175 clks[IMX8ULP_CLK_SPLL3_PFD in imx8ulp_clk_cgc1_init()
233 struct clk_hw **clks; imx8ulp_clk_cgc2_init() local
315 struct clk_hw **clks; imx8ulp_clk_pcc3_init() local
398 struct clk_hw **clks; imx8ulp_clk_pcc4_init() local
453 struct clk_hw **clks; imx8ulp_clk_pcc5_init() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-imx28.c145 static struct clk *clks[clk_max]; variable
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pi in mx28_clocks_init()
[all...]
H A Dclk-imx23.c90 static struct clk *clks[clk_max]; variable
112 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
118 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
119 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
120 clks[gpmi_se in mx23_clocks_init()
[all...]
/kernel/linux/linux-6.6/drivers/clk/mxs/
H A Dclk-imx28.c145 static struct clk *clks[clk_max]; variable
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pi in mx28_clocks_init()
[all...]
H A Dclk-imx23.c90 static struct clk *clks[clk_max]; variable
112 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
118 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
119 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
120 clks[gpmi_se in mx23_clocks_init()
[all...]
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
H A Dclk.c51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
98 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
99 clks[i].parent_name, in hisi_clk_register_fixed_rate()
100 clks[i].flags, in hisi_clk_register_fixed_rate()
101 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
104 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
107 data->clk_data.clks[clks[ in hisi_clk_register_fixed_rate()
120 hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_fixed_factor() argument
150 hisi_clk_register_mux(const struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_mux() argument
188 hisi_clk_register_phase(struct device *dev, const struct hisi_phase_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_phase() argument
212 hisi_clk_register_divider(const struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_divider() argument
250 hisi_clk_register_gate(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_gate() argument
287 hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_gate_sep() argument
316 hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, int nums, struct hisi_clock_data *data) hi6220_clk_register_divider() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
H A Dclk.c51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
98 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
99 clks[i].parent_name, in hisi_clk_register_fixed_rate()
100 clks[i].flags, in hisi_clk_register_fixed_rate()
101 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
104 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
107 data->clk_data.clks[clks[ in hisi_clk_register_fixed_rate()
120 hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_fixed_factor() argument
150 hisi_clk_register_mux(const struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_mux() argument
188 hisi_clk_register_phase(struct device *dev, const struct hisi_phase_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_phase() argument
212 hisi_clk_register_divider(const struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_divider() argument
250 hisi_clk_register_gate(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_gate() argument
287 hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) hisi_clk_register_gate_sep() argument
316 hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, int nums, struct hisi_clock_data *data) hi6220_clk_register_divider() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-bulk.c16 struct clk_bulk_data *clks) in of_clk_bulk_get()
22 clks[i].id = NULL; in of_clk_bulk_get()
23 clks[i].clk = NULL; in of_clk_bulk_get()
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id); in of_clk_bulk_get()
28 clks[i].clk = of_clk_get(np, i); in of_clk_bulk_get()
29 if (IS_ERR(clks[i].clk)) { in of_clk_bulk_get()
30 ret = PTR_ERR(clks[i].clk); in of_clk_bulk_get()
33 clks[i].clk = NULL; in of_clk_bulk_get()
41 clk_bulk_put(i, clks); in of_clk_bulk_get()
47 struct clk_bulk_data **clks) in of_clk_bulk_get_all()
15 of_clk_bulk_get(struct device_node *np, int num_clks, struct clk_bulk_data *clks) of_clk_bulk_get() argument
46 of_clk_bulk_get_all(struct device_node *np, struct clk_bulk_data **clks) of_clk_bulk_get_all() argument
72 clk_bulk_put(int num_clks, struct clk_bulk_data *clks) clk_bulk_put() argument
81 __clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks, bool optional) __clk_bulk_get() argument
114 clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get() argument
121 clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get_optional() argument
128 clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) clk_bulk_put_all() argument
139 clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) clk_bulk_get_all() argument
161 clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_unprepare() argument
176 clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_prepare() argument
211 clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_disable() argument
227 clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_enable() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-bulk.c16 struct clk_bulk_data *clks) in of_clk_bulk_get()
22 clks[i].id = NULL; in of_clk_bulk_get()
23 clks[i].clk = NULL; in of_clk_bulk_get()
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id); in of_clk_bulk_get()
28 clks[i].clk = of_clk_get(np, i); in of_clk_bulk_get()
29 if (IS_ERR(clks[i].clk)) { in of_clk_bulk_get()
30 ret = PTR_ERR(clks[i].clk); in of_clk_bulk_get()
33 clks[i].clk = NULL; in of_clk_bulk_get()
41 clk_bulk_put(i, clks); in of_clk_bulk_get()
47 struct clk_bulk_data **clks) in of_clk_bulk_get_all()
15 of_clk_bulk_get(struct device_node *np, int num_clks, struct clk_bulk_data *clks) of_clk_bulk_get() argument
46 of_clk_bulk_get_all(struct device_node *np, struct clk_bulk_data **clks) of_clk_bulk_get_all() argument
72 clk_bulk_put(int num_clks, struct clk_bulk_data *clks) clk_bulk_put() argument
81 __clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks, bool optional) __clk_bulk_get() argument
114 clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get() argument
121 clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get_optional() argument
128 clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) clk_bulk_put_all() argument
139 clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) clk_bulk_get_all() argument
161 clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_unprepare() argument
176 clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_prepare() argument
211 clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_disable() argument
227 clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_enable() argument
[all...]
/kernel/linux/linux-5.10/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c70 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
403 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
404 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
681 clks[clks_idx_in in mpc512x_clk_setup_mclk()
[all...]
/kernel/linux/linux-6.6/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c70 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
403 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
404 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
681 clks[clks_idx_in in mpc512x_clk_setup_mclk()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
131 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
166 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
191 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
192 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
194 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); in dcn2_update_clocks()
198 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
199 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
201 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks in dcn2_update_clocks()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) in dcn20_update_clocks_update_dentist()
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks in dcn2_update_clocks()
[all...]
/kernel/linux/linux-5.10/drivers/clk/axis/
H A Dclk-artpec6.c43 struct clk **clks; in of_artpec6_clkctrl_setup() local
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
59 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
85 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
92 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
94 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
98 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
100 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
104 clks[ARTPEC6_CLK_DBG_PCL in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; artpec6_clkctrl_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/axis/
H A Dclk-artpec6.c43 struct clk **clks; in of_artpec6_clkctrl_setup() local
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
59 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
85 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
92 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
94 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
98 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
100 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
104 clks[ARTPEC6_CLK_DBG_PCL in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; artpec6_clkctrl_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/socfpga/
H A Dclk-gate-s10.c127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in s10_register_gate() argument
132 const char *parent_name = clks->parent_name; in s10_register_gate()
139 socfpga_clk->hw.reg = regbase + clks->gate_reg; in s10_register_gate()
140 socfpga_clk->hw.bit_idx = clks->gate_idx; in s10_register_gate()
145 socfpga_clk->fixed_div = clks->fixed_div; in s10_register_gate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
152 socfpga_clk->width = clks->div_width; in s10_register_gate()
153 socfpga_clk->shift = clks->div_offset; in s10_register_gate()
155 if (clks in s10_register_gate()
185 agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) agilex_register_gate() argument
[all...]
H A Dclk-periph-s10.c101 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, in s10_register_periph() argument
107 const char *name = clks->name; in s10_register_periph()
108 const char *parent_name = clks->parent_name; in s10_register_periph()
115 periph_clk->hw.reg = reg + clks->offset; in s10_register_periph()
119 init.flags = clks->flags; in s10_register_periph()
121 init.num_parents = clks->num_parents; in s10_register_periph()
124 init.parent_data = clks->parent_data; in s10_register_periph()
137 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, in n5x_register_periph() argument
143 const char *name = clks->name; in n5x_register_periph()
144 const char *parent_name = clks in n5x_register_periph()
172 s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks, void __iomem *regbase) s10_register_cnt_periph() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c79 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
80 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
81 clk_mgr->clks.prev_p_state_change_support = true; in dcn201_init_clocks()
82 clk_mgr->clks.max_supported_dppclk_khz = 1200000; in dcn201_init_clocks()
83 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
103 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
112 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
113 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
119 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
120 clk_mgr_base->clks in dcn201_update_clocks()
[all...]
/kernel/linux/linux-5.10/drivers/clk/zynq/
H A Dclkc.c61 static struct clk *clks[clk_max]; variable
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
198 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
201 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
210 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
212 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
262 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
268 clks[ddrpl in zynq_clk_setup()
[all...]
/kernel/linux/linux-6.6/drivers/clk/zynq/
H A Dclkc.c62 static struct clk *clks[clk_max]; variable
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
197 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
200 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
209 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
211 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
260 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
266 clks[ddrpl in zynq_clk_setup()
[all...]
/kernel/linux/linux-5.10/include/linux/
H A Dclk.h84 * a convenience to consumers which require multiple clks. This
171 * Returns false otherwise. Note that two NULL clks are treated as matching.
274 const struct clk_bulk_data *clks);
283 clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks) in clk_bulk_prepare() argument
301 void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks);
308 const struct clk_bulk_data *clks) in clk_bulk_unprepare()
336 * @clks: the clk_bulk_data table of consumer
339 * operation. If any of the clk cannot be acquired then any clks
353 struct clk_bulk_data *clks);
358 * @clks
307 clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_unprepare() argument
846 clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get() argument
852 clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get_optional() argument
858 clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) clk_bulk_get_all() argument
899 devm_clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) devm_clk_bulk_get() argument
905 devm_clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) devm_clk_bulk_get_optional() argument
911 devm_clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) devm_clk_bulk_get_all() argument
926 clk_bulk_put(int num_clks, struct clk_bulk_data *clks) clk_bulk_put() argument
928 clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) clk_bulk_put_all() argument
937 clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_enable() argument
946 clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_disable() argument
1037 clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_prepare_enable() argument
1051 clk_bulk_disable_unprepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_disable_unprepare() argument
[all...]
/kernel/linux/linux-6.6/include/linux/
H A Dclk.h84 * a convenience to consumers which require multiple clks. This
182 * Returns false otherwise. Note that two NULL clks are treated as matching.
292 const struct clk_bulk_data *clks);
318 clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks) in clk_bulk_prepare() argument
341 void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks);
348 const struct clk_bulk_data *clks) in clk_bulk_unprepare()
376 * @clks: the clk_bulk_data table of consumer
379 * operation. If any of the clk cannot be acquired then any clks
393 struct clk_bulk_data *clks);
398 * @clks
347 clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_unprepare() argument
899 clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get() argument
905 clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) clk_bulk_get_optional() argument
911 clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) clk_bulk_get_all() argument
952 devm_clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) devm_clk_bulk_get() argument
958 devm_clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) devm_clk_bulk_get_optional() argument
964 devm_clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) devm_clk_bulk_get_all() argument
979 clk_bulk_put(int num_clks, struct clk_bulk_data *clks) clk_bulk_put() argument
981 clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) clk_bulk_put_all() argument
990 clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_enable() argument
999 clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_disable() argument
1090 clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks) clk_bulk_prepare_enable() argument
1104 clk_bulk_disable_unprepare(int num_clks, const struct clk_bulk_data *clks) clk_bulk_disable_unprepare() argument
[all...]

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