Lines Matching refs:clks
127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
132 const char *parent_name = clks->parent_name;
139 socfpga_clk->hw.reg = regbase + clks->gate_reg;
140 socfpga_clk->hw.bit_idx = clks->gate_idx;
145 socfpga_clk->fixed_div = clks->fixed_div;
147 if (clks->div_reg)
148 socfpga_clk->div_reg = regbase + clks->div_reg;
152 socfpga_clk->width = clks->div_width;
153 socfpga_clk->shift = clks->div_offset;
155 if (clks->bypass_reg)
156 socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
159 socfpga_clk->bypass_shift = clks->bypass_shift;
161 if (streq(clks->name, "cs_pdbg_clk"))
166 init.name = clks->name;
167 init.flags = clks->flags;
169 init.num_parents = clks->num_parents;
172 init.parent_data = clks->parent_data;
185 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
190 const char *parent_name = clks->parent_name;
197 socfpga_clk->hw.reg = regbase + clks->gate_reg;
198 socfpga_clk->hw.bit_idx = clks->gate_idx;
203 socfpga_clk->fixed_div = clks->fixed_div;
205 if (clks->div_reg)
206 socfpga_clk->div_reg = regbase + clks->div_reg;
210 socfpga_clk->width = clks->div_width;
211 socfpga_clk->shift = clks->div_offset;
213 if (clks->bypass_reg)
214 socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
217 socfpga_clk->bypass_shift = clks->bypass_shift;
219 if (streq(clks->name, "cs_pdbg_clk"))
224 init.name = clks->name;
225 init.flags = clks->flags;
227 init.num_parents = clks->num_parents;
230 init.parent_data = clks->parent_data;