Lines Matching refs:clks
51 clk_data->clk_data.clks = clk_table;
80 clk_data->clk_data.clks = clk_table;
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
98 clk = clk_register_fixed_rate(NULL, clks[i].name,
99 clks[i].parent_name,
100 clks[i].flags,
101 clks[i].fixed_rate);
104 __func__, clks[i].name);
107 data->clk_data.clks[clks[i].id] = clk;
114 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]);
120 int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
128 clk = clk_register_fixed_factor(NULL, clks[i].name,
129 clks[i].parent_name,
130 clks[i].flags, clks[i].mult,
131 clks[i].div);
134 __func__, clks[i].name);
137 data->clk_data.clks[clks[i].id] = clk;
144 clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]);
150 int hisi_clk_register_mux(const struct hisi_mux_clock *clks,
158 u32 mask = BIT(clks[i].width) - 1;
160 clk = clk_register_mux_table(NULL, clks[i].name,
161 clks[i].parent_names,
162 clks[i].num_parents, clks[i].flags,
163 base + clks[i].offset, clks[i].shift,
164 mask, clks[i].mux_flags,
165 clks[i].table, &hisi_clk_lock);
168 __func__, clks[i].name);
172 if (clks[i].alias)
173 clk_register_clkdev(clk, clks[i].alias, NULL);
175 data->clk_data.clks[clks[i].id] = clk;
182 clk_unregister_mux(data->clk_data.clks[clks[i].id]);
189 const struct hisi_phase_clock *clks,
197 clk = clk_register_hisi_phase(dev, &clks[i], base,
201 clks[i].name);
205 data->clk_data.clks[clks[i].id] = clk;
212 int hisi_clk_register_divider(const struct hisi_divider_clock *clks,
220 clk = clk_register_divider_table(NULL, clks[i].name,
221 clks[i].parent_name,
222 clks[i].flags,
223 base + clks[i].offset,
224 clks[i].shift, clks[i].width,
225 clks[i].div_flags,
226 clks[i].table,
230 __func__, clks[i].name);
234 if (clks[i].alias)
235 clk_register_clkdev(clk, clks[i].alias, NULL);
237 data->clk_data.clks[clks[i].id] = clk;
244 clk_unregister_divider(data->clk_data.clks[clks[i].id]);
250 int hisi_clk_register_gate(const struct hisi_gate_clock *clks,
258 clk = clk_register_gate(NULL, clks[i].name,
259 clks[i].parent_name,
260 clks[i].flags,
261 base + clks[i].offset,
262 clks[i].bit_idx,
263 clks[i].gate_flags,
267 __func__, clks[i].name);
271 if (clks[i].alias)
272 clk_register_clkdev(clk, clks[i].alias, NULL);
274 data->clk_data.clks[clks[i].id] = clk;
281 clk_unregister_gate(data->clk_data.clks[clks[i].id]);
287 void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
295 clk = hisi_register_clkgate_sep(NULL, clks[i].name,
296 clks[i].parent_name,
297 clks[i].flags,
298 base + clks[i].offset,
299 clks[i].bit_idx,
300 clks[i].gate_flags,
304 __func__, clks[i].name);
308 if (clks[i].alias)
309 clk_register_clkdev(clk, clks[i].alias, NULL);
311 data->clk_data.clks[clks[i].id] = clk;
316 void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
324 clk = hi6220_register_clkdiv(NULL, clks[i].name,
325 clks[i].parent_name,
326 clks[i].flags,
327 base + clks[i].offset,
328 clks[i].shift,
329 clks[i].width,
330 clks[i].mask_bit,
334 __func__, clks[i].name);
338 if (clks[i].alias)
339 clk_register_clkdev(clk, clks[i].alias, NULL);
341 data->clk_data.clks[clks[i].id] = clk;