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/kernel/linux/linux-5.10/arch/mips/alchemy/common/
H A Dclock.c9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
28 * - memory clock: clk rate to main memory chips, depends on board
48 * found any board yet which uses a different rate.
195 unsigned long rate, in alchemy_clk_aux_setr()
199 unsigned long d = rate; in alchemy_clk_aux_setr()
201 if (rate) in alchemy_clk_aux_setr()
215 unsigned long rate, in alchemy_clk_aux_roundr()
221 if (!rate || !*parent_rate) in alchemy_clk_aux_roundr()
224 mult = rate / (*parent_rat in alchemy_clk_aux_roundr()
194 alchemy_clk_aux_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_aux_setr() argument
214 alchemy_clk_aux_roundr(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) alchemy_clk_aux_roundr() argument
376 alchemy_calc_div(unsigned long rate, unsigned long prate, int scale, int maxdiv, unsigned long *rv) alchemy_calc_div() argument
549 alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_fgv1_setr() argument
670 alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_fgv2_setr() argument
893 alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_csrc_setr() argument
[all...]
/kernel/linux/linux-6.6/arch/mips/alchemy/common/
H A Dclock.c9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
28 * - memory clock: clk rate to main memory chips, depends on board
48 * found any board yet which uses a different rate.
195 unsigned long rate, in alchemy_clk_aux_setr()
199 unsigned long d = rate; in alchemy_clk_aux_setr()
201 if (rate) in alchemy_clk_aux_setr()
215 unsigned long rate, in alchemy_clk_aux_roundr()
221 if (!rate || !*parent_rate) in alchemy_clk_aux_roundr()
224 mult = rate / (*parent_rat in alchemy_clk_aux_roundr()
194 alchemy_clk_aux_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_aux_setr() argument
214 alchemy_clk_aux_roundr(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) alchemy_clk_aux_roundr() argument
376 alchemy_calc_div(unsigned long rate, unsigned long prate, int scale, int maxdiv, unsigned long *rv) alchemy_calc_div() argument
549 alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_fgv1_setr() argument
670 alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_fgv2_setr() argument
893 alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) alchemy_clk_csrc_setr() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/st/
H A Dclkgen-fsyn.c227 * rate - inherits rate from parent. set_rate/round_rate/recalc_rate
323 unsigned long *rate) in clk_fs660c32_vco_get_rate()
327 *rate = input * nd; in clk_fs660c32_vco_get_rate()
336 unsigned long rate = 0; in quadfs_pll_fs660c32_recalc_rate() local
340 if (clk_fs660c32_vco_get_rate(parent_rate, &params, &rate)) in quadfs_pll_fs660c32_recalc_rate()
341 pr_err("%s:%s error calculating rate\n", in quadfs_pll_fs660c32_recalc_rate()
346 return rate; in quadfs_pll_fs660c32_recalc_rate()
379 unsigned long rate, in quadfs_pll_fs660c32_round_rate()
384 if (clk_fs660c32_vco_get_params(*prate, rate, in quadfs_pll_fs660c32_round_rate()
322 clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs, unsigned long *rate) clk_fs660c32_vco_get_rate() argument
378 quadfs_pll_fs660c32_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) quadfs_pll_fs660c32_round_rate() argument
396 quadfs_pll_fs660c32_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) quadfs_pll_fs660c32_set_rate() argument
622 clk_fs660c32_dig_get_rate(unsigned long input, const struct stm_fs *fs, unsigned long *rate) clk_fs660c32_dig_get_rate() argument
782 unsigned long rate = 0; quadfs_find_best_rate() local
797 unsigned long rate = 0; quadfs_recalc_rate() local
817 quadfs_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) quadfs_round_rate() argument
849 quadfs_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) quadfs_set_rate() argument
[all...]
H A Dclkgen-pll.c188 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
193 * rate - rate is fixed. No clk_set_rate support
366 unsigned long *rate) in clk_pll3200c32_get_rate()
371 *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000; in clk_pll3200c32_get_rate()
381 unsigned long rate = 0; in recalc_stm_pll3200c32() local
391 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000; in recalc_stm_pll3200c32()
393 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in recalc_stm_pll3200c32()
395 return rate; in recalc_stm_pll3200c32()
365 clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll, unsigned long *rate) clk_pll3200c32_get_rate() argument
398 round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate, unsigned long *prate) round_rate_stm_pll3200c32() argument
419 set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) set_rate_stm_pll3200c32() argument
521 clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll, unsigned long *rate) clk_pll4600c28_get_rate() argument
537 unsigned long rate; recalc_stm_pll4600c28() local
552 round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate, unsigned long *prate) round_rate_stm_pll4600c28() argument
573 set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) set_rate_stm_pll4600c28() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-sscg-pll.c266 uint64_t rate, int try_bypass) in clk_sscg_pll_find_setup()
275 temp_setup.fout_request = rate; in clk_sscg_pll_find_setup()
279 if (prate == rate) { in clk_sscg_pll_find_setup()
281 setup->fout = rate; in clk_sscg_pll_find_setup()
358 static int clk_sscg_pll_set_rate(struct clk_hw *hw, unsigned long rate, in clk_sscg_pll_set_rate() argument
415 uint64_t rate, in __clk_sscg_pll_determine_rate()
442 ret = clk_sscg_pll_find_setup(setup, req->rate, in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
447 req->best_parent_rate = req->rate; in __clk_sscg_pll_determine_rate()
448 req->rate in __clk_sscg_pll_determine_rate()
264 clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup, uint64_t prate, uint64_t rate, int try_bypass) clk_sscg_pll_find_setup() argument
411 __clk_sscg_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, uint64_t min, uint64_t max, uint64_t rate, int bypass) __clk_sscg_pll_determine_rate() argument
458 uint64_t rate = req->rate; clk_sscg_pll_determine_rate() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/at91/
H A Dclk-sam9x60-pll.c176 unsigned long rate, in sam9x60_frac_pll_compute_mul_frac()
185 if (rate < FCORE_MIN || rate > FCORE_MAX) in sam9x60_frac_pll_compute_mul_frac()
190 * divider that provide the closest rate to the requested one. in sam9x60_frac_pll_compute_mul_frac()
192 nmul = mult_frac(rate, 1, parent_rate); in sam9x60_frac_pll_compute_mul_frac()
194 remainder = rate - tmprate; in sam9x60_frac_pll_compute_mul_frac()
204 /* Check if resulted rate is a valid. */ in sam9x60_frac_pll_compute_mul_frac()
216 static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate, in sam9x60_frac_pll_round_rate() argument
221 return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false); in sam9x60_frac_pll_round_rate()
224 static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate, in sam9x60_frac_pll_set_rate() argument
175 sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, unsigned long rate, unsigned long parent_rate, bool update) sam9x60_frac_pll_compute_mul_frac() argument
325 sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) sam9x60_div_pll_compute_div() argument
368 sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) sam9x60_div_pll_round_rate() argument
376 sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) sam9x60_div_pll_set_rate() argument
[all...]
/kernel/linux/linux-5.10/sound/usb/
H A Dclock.c3 * Clock domain and sample rate management functions
172 * single sample rate, the terminal is connected directly to it in uac_clock_source_is_valid_quirk()
186 * Sample rate changes takes more than 2 seconds for this device. Clock in uac_clock_source_is_valid_quirk()
472 * For all kinds of sample rate settings and other device queries,
474 * clock multipliers and sample rate converters may be specified as
502 struct audioformat *fmt, int rate) in set_sample_rate_v1()
513 /* if endpoint doesn't have sampling rate control, bail out */ in set_sample_rate_v1()
517 data[0] = rate; in set_sample_rate_v1()
518 data[1] = rate >> 8; in set_sample_rate_v1()
519 data[2] = rate >> 1 in set_sample_rate_v1()
500 set_sample_rate_v1(struct snd_usb_audio *chip, int iface, struct usb_host_interface *alts, struct audioformat *fmt, int rate) set_sample_rate_v1() argument
585 set_sample_rate_v2v3(struct snd_usb_audio *chip, int iface, struct usb_host_interface *alts, struct audioformat *fmt, int rate) set_sample_rate_v2v3() argument
679 snd_usb_init_sample_rate(struct snd_usb_audio *chip, int iface, struct usb_host_interface *alts, struct audioformat *fmt, int rate) snd_usb_init_sample_rate() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-sscg-pll.c266 uint64_t rate, int try_bypass) in clk_sscg_pll_find_setup()
275 temp_setup.fout_request = rate; in clk_sscg_pll_find_setup()
279 if (prate == rate) { in clk_sscg_pll_find_setup()
281 setup->fout = rate; in clk_sscg_pll_find_setup()
358 static int clk_sscg_pll_set_rate(struct clk_hw *hw, unsigned long rate, in clk_sscg_pll_set_rate() argument
415 uint64_t rate, in __clk_sscg_pll_determine_rate()
442 ret = clk_sscg_pll_find_setup(setup, req->rate, in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
447 req->best_parent_rate = req->rate; in __clk_sscg_pll_determine_rate()
448 req->rate in __clk_sscg_pll_determine_rate()
264 clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup, uint64_t prate, uint64_t rate, int try_bypass) clk_sscg_pll_find_setup() argument
411 __clk_sscg_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, uint64_t min, uint64_t max, uint64_t rate, int bypass) __clk_sscg_pll_determine_rate() argument
458 uint64_t rate = req->rate; clk_sscg_pll_determine_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/at91/
H A Dclk-usb.c77 tmp_parent_rate = req->rate * div; in at91sam9x5_clk_usb_determine_rate()
84 if (tmp_rate < req->rate) in at91sam9x5_clk_usb_determine_rate()
85 tmp_diff = req->rate - tmp_rate; in at91sam9x5_clk_usb_determine_rate()
87 tmp_diff = tmp_rate - req->rate; in at91sam9x5_clk_usb_determine_rate()
96 if (!best_diff || tmp_rate < req->rate) in at91sam9x5_clk_usb_determine_rate()
107 req->rate = best_rate; in at91sam9x5_clk_usb_determine_rate()
133 static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, in at91sam9x5_clk_usb_set_rate() argument
139 if (!rate) in at91sam9x5_clk_usb_set_rate()
142 div = DIV_ROUND_CLOSEST(parent_rate, rate); in at91sam9x5_clk_usb_set_rate()
159 usb->pms.rate in at91sam9x5_usb_save_context()
322 at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) at91rm9200_clk_usb_round_rate() argument
360 at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) at91rm9200_clk_usb_set_rate() argument
[all...]
/third_party/nghttp2/lib/
H A Dnghttp2_ratelim.c28 void nghttp2_ratelim_init(nghttp2_ratelim *rl, uint64_t burst, uint64_t rate) { in nghttp2_ratelim_init() argument
30 rl->rate = rate; in nghttp2_ratelim_init()
49 if (UINT64_MAX / d < rl->rate) { in nghttp2_ratelim_update()
55 gain = rl->rate * d; in nghttp2_ratelim_update()
/third_party/node/deps/nghttp2/lib/
H A Dnghttp2_ratelim.c28 void nghttp2_ratelim_init(nghttp2_ratelim *rl, uint64_t burst, uint64_t rate) { in nghttp2_ratelim_init() argument
30 rl->rate = rate; in nghttp2_ratelim_init()
49 if (UINT64_MAX / d < rl->rate) { in nghttp2_ratelim_update()
55 gain = rl->rate * d; in nghttp2_ratelim_update()
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
H A Dtx.c45 SET_TX_DESC_DATARATE(txdesc, pkt_info->rate); in rtw_tx_fill_tx_desc()
88 u8 rate; in get_highest_ht_tx_rate() local
91 rate = DESC_RATEMCS15; in get_highest_ht_tx_rate()
93 rate = DESC_RATEMCS7; in get_highest_ht_tx_rate()
95 return rate; in get_highest_ht_tx_rate()
102 u8 rate; in get_highest_vht_tx_rate() local
109 rate = DESC_RATEVHT1SS_MCS7; in get_highest_vht_tx_rate()
112 rate = DESC_RATEVHT1SS_MCS8; in get_highest_vht_tx_rate()
116 rate = DESC_RATEVHT1SS_MCS9; in get_highest_vht_tx_rate()
122 rate in get_highest_vht_tx_rate()
298 u8 rate = DESC_RATE6M; rtw_tx_data_pkt_info_update() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-cpu.c15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
72 struct rockchip_cpuclk *cpuclk, unsigned long rate) in rockchip_get_cpuclk_settings()
79 if (rate in rockchip_get_cpuclk_settings()
71 rockchip_get_cpuclk_settings( struct rockchip_cpuclk *cpuclk, unsigned long rate) rockchip_get_cpuclk_settings() argument
102 rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, const struct rockchip_cpuclk_rate_table *rate) rockchip_cpuclk_set_dividers() argument
124 const struct rockchip_cpuclk_rate_table *rate; rockchip_cpuclk_pre_rate_change() local
187 const struct rockchip_cpuclk_rate_table *rate; rockchip_cpuclk_post_rate_change() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/ux500/
H A Dclk-prcmu.c82 static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate, in clk_prcmu_round_rate() argument
86 return prcmu_round_clock_rate(clk->cg_sel, rate); in clk_prcmu_round_rate()
89 static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate, in clk_prcmu_set_rate() argument
93 return prcmu_set_clock_rate(clk->cg_sel, rate); in clk_prcmu_set_rate()
247 unsigned long rate, in clk_reg_prcmu()
268 /* "rate" can be used for changing the initial frequency */ in clk_reg_prcmu()
269 if (rate) in clk_reg_prcmu()
270 prcmu_set_clock_rate(cg_sel, rate); in clk_reg_prcmu()
294 unsigned long rate, in clk_reg_prcmu_scalable()
297 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flag in clk_reg_prcmu_scalable()
244 clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags, const struct clk_ops *clk_prcmu_ops) clk_reg_prcmu() argument
291 clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) clk_reg_prcmu_scalable() argument
310 clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) clk_reg_prcmu_scalable_rate() argument
338 clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) clk_reg_prcmu_opp_volt_scalable() argument
[all...]
/kernel/linux/linux-5.10/drivers/cpufreq/
H A Ds3c2416-cpufreq.c109 pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n", in s3c2416_cpufreq_set_armdiv()
237 /* When leavin dvs mode, always switch the armdiv to the hclk rate in s3c2416_cpufreq_set_target()
348 unsigned long rate; in s3c2416_cpufreq_driver_init() local
363 * other means to distinguish them other than through the rate of in s3c2416_cpufreq_driver_init()
366 rate = clk_get_rate(msysclk); in s3c2416_cpufreq_driver_init()
367 if (rate == 800 * 1000 * 1000) { in s3c2416_cpufreq_driver_init()
369 rate / 1000); in s3c2416_cpufreq_driver_init()
372 } else if (rate / 1000 == 534000) { in s3c2416_cpufreq_driver_init()
374 rate / 1000); in s3c2416_cpufreq_driver_init()
384 rate / 100 in s3c2416_cpufreq_driver_init()
[all...]
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci-milbeaut.c40 #define MLB_CAL_TOCLKFREQ_MHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000000)
41 #define MLB_CAL_TOCLKFREQ_KHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000)
46 #define MLB_CAL_BCLKFREQ(rate) (rate / MLB_SD_BCLK_I_DIV / 1000000)
144 int rate) in sdhci_milbeaut_bridge_init()
152 if (rate >= MLB_TOCLKFREQ_UNIT_THRES) { in sdhci_milbeaut_bridge_init()
153 clk = MLB_CAL_TOCLKFREQ_MHZ(rate); in sdhci_milbeaut_bridge_init()
158 clk = MLB_CAL_TOCLKFREQ_KHZ(rate); in sdhci_milbeaut_bridge_init()
143 sdhci_milbeaut_bridge_init(struct sdhci_host *host, int rate) sdhci_milbeaut_bridge_init() argument
213 int rate = clk_get_rate(priv->clk); sdhci_milbeaut_init() local
[all...]
/kernel/linux/linux-5.10/sound/pci/echoaudio/
H A Dechoaudio_3g.c145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
149 switch (rate) { in set_spdif_bits()
258 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
265 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); in set_sample_rate()
266 /* Save the rate anyhow */ in set_sample_rate()
267 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
268 chip->sample_rate = rate; in set_sample_rate()
273 if (snd_BUG_ON(rate >= 50000 && in set_sample_rate()
281 switch (rate) { in set_sample_rate()
299 if (rate > 5000 in set_sample_rate()
[all...]
H A Ddarla24_dsp.c97 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
101 switch (rate) { in set_sample_rate()
131 "set_sample_rate: Error, invalid sample rate %d\n", in set_sample_rate()
132 rate); in set_sample_rate()
140 "set_sample_rate: %d clock %d\n", rate, clock); in set_sample_rate()
141 chip->sample_rate = rate; in set_sample_rate()
143 /* Override the sample rate if this card is set to Echo sync. */ in set_sample_rate()
147 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */ in set_sample_rate()
/kernel/linux/linux-5.10/sound/soc/mediatek/mt8183/
H A Dmt8183-dai-adda.c51 unsigned int rate) in adda_dl_rate_transform()
53 switch (rate) { in adda_dl_rate_transform()
77 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", in adda_dl_rate_transform()
78 __func__, rate); in adda_dl_rate_transform()
84 unsigned int rate) in adda_ul_rate_transform()
86 switch (rate) { in adda_ul_rate_transform()
100 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", in adda_ul_rate_transform()
101 __func__, rate); in adda_ul_rate_transform()
357 unsigned int rate = params_rate(params); in mtk_dai_adda_hw_params() local
359 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate in mtk_dai_adda_hw_params()
50 adda_dl_rate_transform(struct mtk_base_afe *afe, unsigned int rate) adda_dl_rate_transform() argument
83 adda_ul_rate_transform(struct mtk_base_afe *afe, unsigned int rate) adda_ul_rate_transform() argument
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsdhci-milbeaut.c40 #define MLB_CAL_TOCLKFREQ_MHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000000)
41 #define MLB_CAL_TOCLKFREQ_KHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000)
46 #define MLB_CAL_BCLKFREQ(rate) (rate / MLB_SD_BCLK_I_DIV / 1000000)
144 int rate) in sdhci_milbeaut_bridge_init()
152 if (rate >= MLB_TOCLKFREQ_UNIT_THRES) { in sdhci_milbeaut_bridge_init()
153 clk = MLB_CAL_TOCLKFREQ_MHZ(rate); in sdhci_milbeaut_bridge_init()
158 clk = MLB_CAL_TOCLKFREQ_KHZ(rate); in sdhci_milbeaut_bridge_init()
143 sdhci_milbeaut_bridge_init(struct sdhci_host *host, int rate) sdhci_milbeaut_bridge_init() argument
213 int rate = clk_get_rate(priv->clk); sdhci_milbeaut_init() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/ux500/
H A Dclk-prcmu.c56 static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate, in clk_prcmu_round_rate() argument
60 return prcmu_round_clock_rate(clk->cg_sel, rate); in clk_prcmu_round_rate()
63 static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate, in clk_prcmu_set_rate() argument
67 return prcmu_set_clock_rate(clk->cg_sel, rate); in clk_prcmu_set_rate()
197 unsigned long rate, in clk_reg_prcmu()
216 /* "rate" can be used for changing the initial frequency */ in clk_reg_prcmu()
217 if (rate) in clk_reg_prcmu()
218 prcmu_set_clock_rate(cg_sel, rate); in clk_reg_prcmu()
242 unsigned long rate, in clk_reg_prcmu_scalable()
245 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flag in clk_reg_prcmu_scalable()
194 clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags, const struct clk_ops *clk_prcmu_ops) clk_reg_prcmu() argument
239 clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) clk_reg_prcmu_scalable() argument
258 clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) clk_reg_prcmu_scalable_rate() argument
286 clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) clk_reg_prcmu_opp_volt_scalable() argument
[all...]
/kernel/linux/linux-6.6/sound/pci/echoaudio/
H A Dechoaudio_3g.c145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
149 switch (rate) { in set_spdif_bits()
258 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
265 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); in set_sample_rate()
266 /* Save the rate anyhow */ in set_sample_rate()
267 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
268 chip->sample_rate = rate; in set_sample_rate()
273 if (snd_BUG_ON(rate >= 50000 && in set_sample_rate()
281 switch (rate) { in set_sample_rate()
299 if (rate > 5000 in set_sample_rate()
[all...]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8183/
H A Dmt8183-dai-adda.c51 unsigned int rate) in adda_dl_rate_transform()
53 switch (rate) { in adda_dl_rate_transform()
77 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", in adda_dl_rate_transform()
78 __func__, rate); in adda_dl_rate_transform()
84 unsigned int rate) in adda_ul_rate_transform()
86 switch (rate) { in adda_ul_rate_transform()
100 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", in adda_ul_rate_transform()
101 __func__, rate); in adda_ul_rate_transform()
358 unsigned int rate = params_rate(params); in mtk_dai_adda_hw_params() local
360 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate in mtk_dai_adda_hw_params()
50 adda_dl_rate_transform(struct mtk_base_afe *afe, unsigned int rate) adda_dl_rate_transform() argument
83 adda_ul_rate_transform(struct mtk_base_afe *afe, unsigned int rate) adda_ul_rate_transform() argument
[all...]
/third_party/node/benchmark/
H A Dcommon.js273 const rate = operations / (Number(elapsed) / 1e9);
274 this.report(rate, elapsed);
277 report(rate, elapsed) {
281 rate,
304 let rate = data.rate.toString().split('.');
305 rate[0] = rate[0].replace(/(\d)(?=(?:\d\d\d)+(?!\d))/g, '$1,');
306 rate = (rate[
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dclps711x-timer.c32 unsigned long rate = clk_get_rate(clock); in clps711x_clksrc_init() local
36 clocksource_mmio_init(tcd, "clps711x-clocksource", rate, 300, 16, in clps711x_clksrc_init()
39 sched_clock_register(clps711x_sched_clock_read, 16, rate); in clps711x_clksrc_init()
55 unsigned long rate; in _clps711x_clkevt_init() local
61 rate = clk_get_rate(clock); in _clps711x_clkevt_init()
64 writew(DIV_ROUND_CLOSEST(rate, HZ), base); in _clps711x_clkevt_init()

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