Lines Matching refs:rate
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
28 * - memory clock: clk rate to main memory chips, depends on board
48 * found any board yet which uses a different rate.
195 unsigned long rate,
199 unsigned long d = rate;
201 if (rate)
215 unsigned long rate,
221 if (!rate || !*parent_rate)
224 mult = rate / (*parent_rate);
289 /* Peripheral clock runs at half the rate of sysbus clk */
376 static long alchemy_calc_div(unsigned long rate, unsigned long prate,
381 div1 = prate / rate;
382 if ((prate / div1) > rate)
416 * the one that gets closest to but not over the requested rate.
433 if (pr < req->rate)
437 tdv = alchemy_calc_div(req->rate, pr, scale, maxdiv, NULL);
439 diff = req->rate - nr;
440 if (nr > req->rate)
453 /* if we couldn't get the exact rate we wanted from the enabled
455 * to give us a rate we can divide down to the requested rate.
459 tpr = req->rate * j;
464 tdv = alchemy_calc_div(req->rate, pr, scale, maxdiv,
467 diff = req->rate - nr;
468 if (nr > req->rate)
486 req->rate = br;
549 static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
556 if (!rate || !parent_rate || rate > (parent_rate / 2))
558 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
670 static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
677 if (!rate || !parent_rate || rate > parent_rate)
681 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
893 static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
900 if (!rate || !parent_rate || rate > parent_rate)
903 d = (parent_rate + (rate / 2)) / rate;
1078 /* peripheral clock: runs at half rate of sysbus clk */