Lines Matching refs:rate
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
72 struct rockchip_cpuclk *cpuclk, unsigned long rate)
79 if (rate == rate_table[i].prate)
103 const struct rockchip_cpuclk_rate_table *rate)
108 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {
109 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];
124 const struct rockchip_cpuclk_rate_table *rate;
128 /* check validity of the new rate */
129 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
130 if (!rate) {
131 pr_err("%s: Invalid rate : %lu for cpuclk\n",
162 pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
187 const struct rockchip_cpuclk_rate_table *rate;
190 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
191 if (!rate) {
192 pr_err("%s: Invalid rate : %lu for cpuclk\n",
200 rockchip_cpuclk_set_dividers(cpuclk, rate);
203 * post-rate change event, re-mux to primary parent and remove dividers.
217 rockchip_cpuclk_set_dividers(cpuclk, rate);
271 /* only allow rate changes when we have a rate table */