Lines Matching refs:rate
176 unsigned long rate,
185 if (rate < FCORE_MIN || rate > FCORE_MAX)
190 * divider that provide the closest rate to the requested one.
192 nmul = mult_frac(rate, 1, parent_rate);
194 remainder = rate - tmprate;
204 /* Check if resulted rate is a valid. */
216 static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate,
221 return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
224 static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
229 return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
327 unsigned long rate)
336 if (!rate)
339 if (rate < characteristics->output[0].min ||
340 rate > characteristics->output[0].max)
344 tmp_parent_rate = clk_hw_round_rate(parent, rate * divid);
349 tmp_diff = abs(rate - tmp_rate);
368 static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate,
373 return sam9x60_div_pll_compute_div(core, parent_rate, rate);
376 static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
382 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
442 * case we need to set the minimum rate for it. Otherwise
444 * its rate leading to enabling this PLL with unsupported
445 * rate. This will lead to PLL not being locked at all.