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/third_party/skia/src/gpu/vk/
H A DGrVkMemory.cpp7 #include "src/gpu/vk/GrVkMemory.h"
16 #include "src/gpu/vk/GrVkGpu.h"
17 #include "src/gpu/vk/GrVkUtil.h"
24 static bool FindMemoryType(GrVkGpu *gpu, uint32_t typeFilter, VkMemoryPropertyFlags properties, uint32_t &typeIndex) in FindMemoryType() argument
26 VkPhysicalDevice physicalDevice = gpu->physicalDevice(); in FindMemoryType()
28 VK_CALL(gpu, GetPhysicalDeviceMemoryProperties(physicalDevice, &memProperties)); in FindMemoryType()
44 bool GrVkMemory::AllocAndBindBufferMemory(GrVkGpu* gpu, argument
53 GrVkMemoryAllocator* allocator = gpu->memoryAllocator();
57 bool shouldPersistentlyMapCpuToGpu = gpu->vkCaps().shouldPersistentlyMapCpuToGpuBuffers();
68 if (!gpu
90 ImportAndBindBufferMemory(GrVkGpu* gpu, OH_NativeBuffer *nativeBuffer, VkBuffer buffer, GrVkAlloc* alloc) global() argument
146 FreeBufferMemory(const GrVkGpu* gpu, const GrVkAlloc& alloc) global() argument
162 AllocAndBindImageMemory(GrVkGpu* gpu, VkImage image, GrMemoryless memoryless, GrVkAlloc* alloc, int memorySize) global() argument
231 FreeImageMemory(const GrVkGpu* gpu, const GrVkAlloc& alloc) global() argument
243 MapAlloc(GrVkGpu* gpu, const GrVkAlloc& alloc) global() argument
258 UnmapAlloc(const GrVkGpu* gpu, const GrVkAlloc& alloc) global() argument
290 FlushMappedAlloc(GrVkGpu* gpu, const GrVkAlloc& alloc, VkDeviceSize offset, VkDeviceSize size) global() argument
305 InvalidateMappedAlloc(GrVkGpu* gpu, const GrVkAlloc& alloc, VkDeviceSize offset, VkDeviceSize size) global() argument
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H A DGrVkCommandBuffer.h12 #include "include/gpu/vk/GrVkTypes.h"
13 #include "src/gpu/GrManagedResource.h"
14 #include "src/gpu/GrRefCnt.h"
15 #include "src/gpu/vk/GrVkGpu.h"
16 #include "src/gpu/vk/GrVkSemaphore.h"
17 #include "src/gpu/vk/GrVkUtil.h"
40 void pipelineBarrier(const GrVkGpu* gpu,
48 void bindInputBuffer(GrVkGpu* gpu, uint32_t binding, sk_sp<const GrBuffer> buffer);
50 void bindIndexBuffer(GrVkGpu* gpu, sk_sp<const GrBuffer> buffer);
52 void bindPipeline(const GrVkGpu* gpu, sk_s
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H A DGrVkCommandBuffer.cpp8 #include "src/gpu/vk/GrVkCommandBuffer.h"
12 #include "src/gpu/vk/GrVkBuffer.h"
13 #include "src/gpu/vk/GrVkCommandPool.h"
14 #include "src/gpu/vk/GrVkFramebuffer.h"
15 #include "src/gpu/vk/GrVkGpu.h"
16 #include "src/gpu/vk/GrVkImage.h"
17 #include "src/gpu/vk/GrVkImageView.h"
18 #include "src/gpu/vk/GrVkPipeline.h"
19 #include "src/gpu/vk/GrVkPipelineState.h"
20 #include "src/gpu/v
46 freeGPUData(const GrGpu* gpu, VkCommandPool cmdPool) const freeGPUData() argument
80 pipelineBarrier(const GrVkGpu* gpu, const GrManagedResource* resource, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, bool byRegion, BarrierType barrierType, void* barrier) pipelineBarrier() argument
150 submitPipelineBarriers(const GrVkGpu* gpu, bool forSelfDependency) submitPipelineBarriers() argument
181 bindInputBuffer(GrVkGpu* gpu, uint32_t binding, sk_sp<const GrBuffer> buffer) bindInputBuffer() argument
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H A DGrVkImage.cpp8 #include "src/gpu/vk/GrVkImage.h"
10 #include "src/gpu/vk/GrVkGpu.h"
11 #include "src/gpu/vk/GrVkImageView.h"
12 #include "src/gpu/vk/GrVkMemory.h"
13 #include "src/gpu/vk/GrVkTexture.h"
14 #include "src/gpu/vk/GrVkUtil.h"
19 sk_sp<GrVkImage> GrVkImage::MakeStencil(GrVkGpu* gpu, in MakeStencil() argument
25 return GrVkImage::Make(gpu, in MakeStencil()
37 sk_sp<GrVkImage> GrVkImage::MakeMSAA(GrVkGpu* gpu, in MakeMSAA() argument
51 return GrVkImage::Make(gpu, in MakeMSAA()
63 MakeTexture(GrVkGpu* gpu, SkISize dimensions, VkFormat format, uint32_t mipLevels, GrRenderable renderable, int numSamples, SkBudgeted budgeted, GrProtected isProtected) MakeTexture() argument
93 make_views(GrVkGpu* gpu, const GrVkImageInfo& info, GrAttachment::UsageFlags attachmentUsages, sk_sp<const GrVkImageView>* framebufferView, sk_sp<const GrVkImageView>* textureView) make_views() argument
131 Make(GrVkGpu* gpu, SkISize dimensions, UsageFlags attachmentUsages, int sampleCnt, VkFormat format, uint32_t mipLevels, VkImageUsageFlags vkUsageFlags, GrProtected isProtected, GrMemoryless memoryless, SkBudgeted budgeted) Make() argument
176 MakeWrapped(GrVkGpu* gpu, SkISize dimensions, const GrVkImageInfo& info, sk_sp<GrBackendSurfaceMutableStateImpl> mutableState, UsageFlags attachmentUsages, GrWrapOwnership ownership, GrWrapCacheable cacheable, bool forSecondaryCB) MakeWrapped() argument
209 DestroyAndFreeImageMemory(const GrVkGpu* gpu, const GrVkAlloc& alloc, const VkImage& image) DestroyAndFreeImageMemory() argument
215 GrVkImage(GrVkGpu* gpu, SkISize dimensions, UsageFlags supportedUsages, const GrVkImageInfo& info, sk_sp<GrBackendSurfaceMutableStateImpl> mutableState, sk_sp<const GrVkImageView> framebufferView, sk_sp<const GrVkImageView> textureView, SkBudgeted budgeted) GrVkImage() argument
246 GrVkImage(GrVkGpu* gpu, SkISize dimensions, UsageFlags supportedUsages, const GrVkImageInfo& info, sk_sp<GrBackendSurfaceMutableStateImpl> mutableState, sk_sp<const GrVkImageView> framebufferView, sk_sp<const GrVkImageView> textureView, GrBackendObjectOwnership ownership, GrWrapCacheable cacheable, bool forSecondaryCB) GrVkImage() argument
272 init(GrVkGpu* gpu, bool forSecondaryCB) init() argument
381 setImageLayoutAndQueueIndex(const GrVkGpu* gpu, VkImageLayout newLayout, VkAccessFlags dstAccessMask, VkPipelineStageFlags dstStageMask, bool byRegion, uint32_t newQueueFamilyIndex) setImageLayoutAndQueueIndex() argument
473 InitImageInfo(GrVkGpu* gpu, const ImageDesc& imageDesc, GrVkImageInfo* info) InitImageInfo() argument
555 DestroyImageInfo(const GrVkGpu* gpu, GrVkImageInfo* info) DestroyImageInfo() argument
566 prepareForPresent(GrVkGpu* gpu) prepareForPresent() argument
578 prepareForExternal(GrVkGpu* gpu) prepareForExternal() argument
627 write_input_desc_set(GrVkGpu* gpu, VkImageView view, VkImageLayout layout, VkDescriptorSet descSet) write_input_desc_set() argument
653 inputDescSetForBlending(GrVkGpu* gpu) inputDescSetForBlending() argument
674 inputDescSetForMSAALoad(GrVkGpu* gpu) inputDescSetForMSAALoad() argument
710 setCurrentQueueFamilyToGraphicsQueue(GrVkGpu* gpu) setCurrentQueueFamilyToGraphicsQueue() argument
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H A DGrVkMSAALoadManager.cpp8 #include "src/gpu/vk/GrVkMSAALoadManager.h"
10 #include "include/gpu/GrDirectContext.h"
12 #include "src/gpu/GrDirectContextPriv.h"
13 #include "src/gpu/GrResourceProvider.h"
14 #include "src/gpu/vk/GrVkBuffer.h"
15 #include "src/gpu/vk/GrVkCommandBuffer.h"
16 #include "src/gpu/vk/GrVkDescriptorSet.h"
17 #include "src/gpu/vk/GrVkGpu.h"
18 #include "src/gpu/vk/GrVkImageView.h"
19 #include "src/gpu/v
31 createMSAALoadProgram(GrVkGpu* gpu) createMSAALoadProgram() argument
116 loadMSAAFromResolve(GrVkGpu* gpu, GrVkCommandBuffer* commandBuffer, const GrVkRenderPass& renderPass, GrAttachment* dst, GrVkImage* src, const SkIRect& rect) loadMSAAFromResolve() argument
217 destroyResources(GrVkGpu* gpu) destroyResources() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/etnaviv/
H A Detnaviv_sched.c28 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
37 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
42 drm_sched_stop(&gpu->sched, sched_job); in etnaviv_sched_timedout_job()
56 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
57 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
58 if (gpu->state == ETNA_GPU_STATE_RUNNING && in etnaviv_sched_timedout_job()
59 (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
61 gpu in etnaviv_sched_timedout_job()
101 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_sched_push_job() local
133 etnaviv_sched_init(struct etnaviv_gpu *gpu) etnaviv_sched_init() argument
147 etnaviv_sched_fini(struct etnaviv_gpu *gpu) etnaviv_sched_fini() argument
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H A Detnaviv_buffer.c90 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
95 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
103 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
105 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
116 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
122 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
124 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump()
152 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
159 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_reserve()
163 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument
180 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr) etnaviv_buffer_config_mmuv2() argument
215 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id) etnaviv_buffer_config_pta() argument
233 etnaviv_buffer_end(struct etnaviv_gpu *gpu) etnaviv_buffer_end() argument
301 etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) etnaviv_sync_point_queue() argument
340 etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, struct etnaviv_iommu_context *mmu_context, unsigned int event, struct etnaviv_cmdbuf *cmdbuf) etnaviv_buffer_queue() argument
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H A Detnaviv_perfmon.c18 u32 (*sample)(struct etnaviv_gpu *gpu,
40 static u32 perf_reg_read(struct etnaviv_gpu *gpu, in perf_reg_read() argument
44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
49 static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe) in pipe_select() argument
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
57 static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu, in pipe_perf_reg_read() argument
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
65 for (i = 0; i < gpu->identity.pixel_pipes; i++) { in pipe_perf_reg_read()
66 pipe_select(gpu, cloc in pipe_perf_reg_read()
76 pipe_reg_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) pipe_reg_read() argument
95 hi_total_cycle_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) hi_total_cycle_read() argument
109 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) hi_total_idle_cycle_read() argument
462 num_pm_domains(const struct etnaviv_gpu *gpu) num_pm_domains() argument
476 pm_domain(const struct etnaviv_gpu *gpu, unsigned int index) pm_domain() argument
499 etnaviv_pm_query_dom(struct etnaviv_gpu *gpu, struct drm_etnaviv_pm_domain *domain) etnaviv_pm_query_dom() argument
523 etnaviv_pm_query_sig(struct etnaviv_gpu *gpu, struct drm_etnaviv_pm_signal *signal) etnaviv_pm_query_sig() argument
569 etnaviv_perfmon_process(struct etnaviv_gpu *gpu, const struct etnaviv_perfmon_request *pmr, u32 exec_state) etnaviv_perfmon_process() argument
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H A Detnaviv_gpu.h89 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
166 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
168 writel(data, gpu->mmio + reg); in gpu_write()
171 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
173 return readl(gpu->mmio + reg); in gpu_read()
176 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg) in gpu_fix_power_address() argument
179 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
180 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
186 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write_power() argument
188 writel(data, gpu in gpu_write_power()
191 gpu_read_power(struct etnaviv_gpu *gpu, u32 reg) gpu_read_power() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
H A Detnaviv_buffer.c89 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
94 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
102 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
104 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
115 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
121 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
123 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump()
151 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
158 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_reserve()
162 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument
179 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr) etnaviv_buffer_config_mmuv2() argument
214 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id) etnaviv_buffer_config_pta() argument
232 etnaviv_buffer_end(struct etnaviv_gpu *gpu) etnaviv_buffer_end() argument
300 etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) etnaviv_sync_point_queue() argument
339 etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, struct etnaviv_iommu_context *mmu_context, unsigned int event, struct etnaviv_cmdbuf *cmdbuf) etnaviv_buffer_queue() argument
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H A Detnaviv_sched.c80 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
88 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
93 drm_sched_stop(&gpu->sched, sched_job); in etnaviv_sched_timedout_job()
107 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
108 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
109 if (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
111 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job()
112 gpu in etnaviv_sched_timedout_job()
184 etnaviv_sched_init(struct etnaviv_gpu *gpu) etnaviv_sched_init() argument
197 etnaviv_sched_fini(struct etnaviv_gpu *gpu) etnaviv_sched_fini() argument
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H A Detnaviv_perfmon.c18 u32 (*sample)(struct etnaviv_gpu *gpu,
40 static u32 perf_reg_read(struct etnaviv_gpu *gpu, in perf_reg_read() argument
44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
49 static u32 pipe_reg_read(struct etnaviv_gpu *gpu, in pipe_reg_read() argument
53 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
57 for (i = 0; i < gpu->identity.pixel_pipes; i++) { in pipe_reg_read()
60 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read()
61 gpu_write(gpu, domain->profile_config, signal->data); in pipe_reg_read()
62 value += gpu_read(gpu, domai in pipe_reg_read()
73 hi_total_cycle_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) hi_total_cycle_read() argument
87 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) hi_total_idle_cycle_read() argument
430 num_pm_domains(const struct etnaviv_gpu *gpu) num_pm_domains() argument
444 pm_domain(const struct etnaviv_gpu *gpu, unsigned int index) pm_domain() argument
467 etnaviv_pm_query_dom(struct etnaviv_gpu *gpu, struct drm_etnaviv_pm_domain *domain) etnaviv_pm_query_dom() argument
491 etnaviv_pm_query_sig(struct etnaviv_gpu *gpu, struct drm_etnaviv_pm_signal *signal) etnaviv_pm_query_sig() argument
537 etnaviv_perfmon_process(struct etnaviv_gpu *gpu, const struct etnaviv_perfmon_request *pmr, u32 exec_state) etnaviv_perfmon_process() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
25 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a2xx_submit()
51 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
56 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a2xx_me_init()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
104 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
105 return a2xx_idle(gpu); in a2xx_me_init()
108 a2xx_hw_init(struct msm_gpu *gpu) a2xx_hw_init() argument
266 a2xx_recover(struct msm_gpu *gpu) a2xx_recover() argument
287 a2xx_destroy(struct msm_gpu *gpu) a2xx_destroy() argument
299 a2xx_idle(struct msm_gpu *gpu) a2xx_idle() argument
317 a2xx_irq(struct msm_gpu *gpu) a2xx_irq() argument
448 a2xx_dump(struct msm_gpu *gpu) a2xx_dump() argument
455 a2xx_gpu_state_get(struct msm_gpu *gpu) a2xx_gpu_state_get() argument
470 a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) a2xx_create_address_space() argument
484 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a2xx_get_rptr() argument
520 struct msm_gpu *gpu; a2xx_gpu_init() local
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H A Da5xx_debugfs.c14 static void pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument
21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
27 static void me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
40 static void meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
53 static void roq_print(struct msm_gpu *gpu, struc argument
97 struct msm_gpu *gpu = priv->gpu; reset_set() local
144 a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor) a5xx_debugfs_init() argument
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H A Da6xx_gpu_state.c120 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
123 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
133 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
136 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
150 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova); in a6xx_crashdumper_run()
152 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
154 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
157 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
163 static int debugbus_read(struct msm_gpu *gpu, u3 argument
211 vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, u32 reg, int count, u32 *data) vbif_debugbus_read() argument
235 a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_gpu_state_obj *obj) a6xx_get_vbif_debugbus_block() argument
289 a6xx_get_debugbus_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_debugbus_block *block, struct a6xx_gpu_state_obj *obj) a6xx_get_debugbus_block() argument
325 a6xx_get_debugbus(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_get_debugbus() argument
465 a6xx_get_dbgahb_cluster(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_dbgahb_cluster *dbgahb, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_dbgahb_cluster() argument
511 a6xx_get_dbgahb_clusters(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_dbgahb_clusters() argument
533 a6xx_get_cluster(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_cluster *cluster, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_cluster() argument
593 a6xx_get_clusters(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_clusters() argument
613 a6xx_get_shader_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_shader_block *block, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_shader_block() argument
644 a6xx_get_shaders(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_shaders() argument
664 a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_crashdumper_hlsq_registers() argument
702 a6xx_get_crashdumper_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_crashdumper_registers() argument
745 a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj) a6xx_get_ahb_gpu_registers() argument
776 _a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj, bool rscc) _a6xx_get_gmu_registers() argument
813 a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_get_gmu_registers() argument
866 a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_snapshot_gmu_hfi_history() argument
886 a6xx_get_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_registers() argument
945 a6xx_get_cp_roq_size(struct msm_gpu *gpu) a6xx_get_cp_roq_size() argument
952 a6xx_get_indexed_regs(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_indexed_registers *indexed, struct a6xx_gpu_state_obj *obj) a6xx_get_indexed_regs() argument
975 a6xx_get_indexed_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_get_indexed_registers() argument
1026 a6xx_gpu_state_get(struct msm_gpu *gpu) a6xx_gpu_state_get() argument
1310 a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) a6xx_show() argument
[all...]
H A Dadreno_gpu.c30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
179 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
195 adreno_create_address_space(struct msm_gpu *gpu, in adreno_create_address_space() argument
202 adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, unsigned long quirks) adreno_iommu_create_address_space() argument
236 adreno_private_address_space_size(struct msm_gpu *gpu) adreno_private_address_space_size() argument
253 adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]) adreno_fault_handler() argument
309 adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len) adreno_get_param() argument
378 adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t value, uint32_t len) adreno_set_param() argument
538 adreno_fw_create_bo(struct msm_gpu *gpu, const struct firmware *fw, u64 *iova) adreno_fw_create_bo() argument
557 adreno_hw_init(struct msm_gpu *gpu) adreno_hw_init() argument
587 struct msm_gpu *gpu = &adreno_gpu->base; get_rptr() local
592 adreno_active_ring(struct msm_gpu *gpu) adreno_active_ring() argument
597 adreno_recover(struct msm_gpu *gpu) adreno_recover() argument
615 adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) adreno_flush() argument
635 adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) adreno_idle() argument
651 adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) adreno_gpu_state_get() argument
830 adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) adreno_show() argument
907 adreno_dump_info(struct msm_gpu *gpu) adreno_dump_info() argument
929 adreno_dump(struct msm_gpu *gpu) adreno_dump() argument
969 adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) adreno_get_pwrlevels() argument
1064 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_init() local
1120 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_cleanup() local
[all...]
/third_party/mesa3d/src/broadcom/common/
H A Dv3d_cpu_tiling.h32 void *gpu, uint32_t gpu_stride) in v3d_load_utile()
40 "vldm %[gpu], {q0, q1, q2, q3}\n" in v3d_load_utile()
53 : [gpu] "r"(gpu), in v3d_load_utile()
63 "vldm %[gpu], {q0, q1, q2, q3};\n" in v3d_load_utile()
78 : [gpu] "r"(gpu), in v3d_load_utile()
89 "ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [%[gpu]]\n" in v3d_load_utile()
102 : [gpu] "r"(gpu), in v3d_load_utile()
31 v3d_load_utile(void *cpu, uint32_t cpu_stride, void *gpu, uint32_t gpu_stride) v3d_load_utile() argument
141 v3d_store_utile(void *gpu, uint32_t gpu_stride, void *cpu, uint32_t cpu_stride) v3d_store_utile() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
15 struct msm_drm_private *priv = gpu->dev->dev_private; in a2xx_submit()
52 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
55 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
57 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
98 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
99 return a2xx_idle(gpu); in a2xx_me_init()
102 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument
248 a2xx_recover(struct msm_gpu *gpu) a2xx_recover() argument
269 a2xx_destroy(struct msm_gpu *gpu) a2xx_destroy() argument
281 a2xx_idle(struct msm_gpu *gpu) a2xx_idle() argument
299 a2xx_irq(struct msm_gpu *gpu) a2xx_irq() argument
430 a2xx_dump(struct msm_gpu *gpu) a2xx_dump() argument
437 a2xx_gpu_state_get(struct msm_gpu *gpu) a2xx_gpu_state_get() argument
452 a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) a2xx_create_address_space() argument
466 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a2xx_get_rptr() argument
501 struct msm_gpu *gpu; a2xx_gpu_init() local
[all...]
H A Dadreno_gpu.c24 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
27 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
79 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
84 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
134 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
170 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
172 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
173 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
185 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
189 adreno_iommu_create_address_space(struct msm_gpu *gpu, in adreno_iommu_create_address_space() argument
220 adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) adreno_get_param() argument
374 adreno_fw_create_bo(struct msm_gpu *gpu, const struct firmware *fw, u64 *iova) adreno_fw_create_bo() argument
393 adreno_hw_init(struct msm_gpu *gpu) adreno_hw_init() argument
425 struct msm_gpu *gpu = &adreno_gpu->base; get_rptr() local
430 adreno_active_ring(struct msm_gpu *gpu) adreno_active_ring() argument
435 adreno_recover(struct msm_gpu *gpu) adreno_recover() argument
453 adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) adreno_flush() argument
473 adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) adreno_idle() argument
489 adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) adreno_gpu_state_get() argument
661 adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) adreno_show() argument
723 adreno_dump_info(struct msm_gpu *gpu) adreno_dump_info() argument
746 adreno_dump(struct msm_gpu *gpu) adreno_dump() argument
818 adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) adreno_get_pwrlevels() argument
901 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_init() local
955 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_cleanup() local
[all...]
H A Da5xx_debugfs.c14 static void pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument
21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
27 static void me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
40 static void meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
53 static void roq_print(struct msm_gpu *gpu, struc argument
97 struct msm_gpu *gpu = priv->gpu; reset_set() local
144 a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor) a5xx_debugfs_init() argument
[all...]
H A Da6xx_gpu_state.c112 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
115 dumper->ptr = msm_gem_kernel_new_locked(gpu->dev, in a6xx_crashdumper_init()
116 SZ_1M, MSM_BO_UNCACHED, gpu->aspace, in a6xx_crashdumper_init()
125 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
128 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
142 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO, in a6xx_crashdumper_run()
145 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
147 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
150 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
156 static int debugbus_read(struct msm_gpu *gpu, u3 argument
204 vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, u32 reg, int count, u32 *data) vbif_debugbus_read() argument
228 a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_gpu_state_obj *obj) a6xx_get_vbif_debugbus_block() argument
282 a6xx_get_debugbus_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_debugbus_block *block, struct a6xx_gpu_state_obj *obj) a6xx_get_debugbus_block() argument
318 a6xx_get_debugbus(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_get_debugbus() argument
446 a6xx_get_dbgahb_cluster(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_dbgahb_cluster *dbgahb, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_dbgahb_cluster() argument
492 a6xx_get_dbgahb_clusters(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_dbgahb_clusters() argument
514 a6xx_get_cluster(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_cluster *cluster, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_cluster() argument
563 a6xx_get_clusters(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_clusters() argument
583 a6xx_get_shader_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_shader_block *block, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_shader_block() argument
614 a6xx_get_shaders(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_shaders() argument
634 a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_crashdumper_hlsq_registers() argument
672 a6xx_get_crashdumper_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj, struct a6xx_crashdumper *dumper) a6xx_get_crashdumper_registers() argument
710 a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj) a6xx_get_ahb_gpu_registers() argument
736 _a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, struct a6xx_gpu_state_obj *obj, bool rscc) _a6xx_get_gmu_registers() argument
773 a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_get_gmu_registers() argument
804 a6xx_get_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) a6xx_get_registers() argument
850 a6xx_get_indexed_regs(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_indexed_registers *indexed, struct a6xx_gpu_state_obj *obj) a6xx_get_indexed_regs() argument
870 a6xx_get_indexed_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) a6xx_get_indexed_registers() argument
906 a6xx_gpu_state_get(struct msm_gpu *gpu) a6xx_gpu_state_get() argument
1156 a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) a6xx_show() argument
[all...]
/third_party/skia/src/gpu/d3d/
H A DGrD3DCpuDescriptorManager.cpp8 #include "src/gpu/d3d/GrD3DCpuDescriptorManager.h"
10 #include "src/gpu/d3d/GrD3DGpu.h"
12 GrD3DCpuDescriptorManager::GrD3DCpuDescriptorManager(GrD3DGpu* gpu) in GrD3DCpuDescriptorManager() argument
13 : fRTVDescriptorPool(gpu, D3D12_DESCRIPTOR_HEAP_TYPE_RTV) in GrD3DCpuDescriptorManager()
14 , fDSVDescriptorPool(gpu, D3D12_DESCRIPTOR_HEAP_TYPE_DSV) in GrD3DCpuDescriptorManager()
15 , fShaderViewDescriptorPool(gpu, D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV) in GrD3DCpuDescriptorManager()
16 , fSamplerDescriptorPool(gpu, D3D12_DESCRIPTOR_HEAP_TYPE_SAMPLER) {} in GrD3DCpuDescriptorManager()
19 GrD3DGpu* gpu, ID3D12Resource* textureResource) { in createRenderTargetView()
20 const GrD3DDescriptorHeap::CPUHandle& descriptor = fRTVDescriptorPool.allocateHandle(gpu); in createRenderTargetView()
21 gpu in createRenderTargetView()
18 createRenderTargetView( GrD3DGpu* gpu, ID3D12Resource* textureResource) createRenderTargetView() argument
30 createDepthStencilView( GrD3DGpu* gpu, ID3D12Resource* textureResource) createDepthStencilView() argument
42 createConstantBufferView( GrD3DGpu* gpu, ID3D12Resource* bufferResource, size_t offset, size_t size) createConstantBufferView() argument
53 createShaderResourceView( GrD3DGpu* gpu, ID3D12Resource* resource, unsigned int mostDetailedMip, unsigned int mipLevels) createShaderResourceView() argument
70 createUnorderedAccessView( GrD3DGpu* gpu, ID3D12Resource* resource, unsigned int mipSlice) createUnorderedAccessView() argument
92 createSampler( GrD3DGpu* gpu, D3D12_FILTER filter, float maxLOD, D3D12_TEXTURE_ADDRESS_MODE addressModeU, D3D12_TEXTURE_ADDRESS_MODE addressModeV) createSampler() argument
122 Make( GrD3DGpu* gpu, D3D12_DESCRIPTOR_HEAP_TYPE type, unsigned int numDescriptors) Make() argument
150 HeapPool(GrD3DGpu* gpu, D3D12_DESCRIPTOR_HEAP_TYPE heapType) HeapPool() argument
158 allocateHandle( GrD3DGpu* gpu) allocateHandle() argument
[all...]
H A DGrD3DTexture.cpp8 #include "src/gpu/d3d/GrD3DTexture.h"
10 #include "src/gpu/GrTexture.h"
11 #include "src/gpu/d3d/GrD3DGpu.h"
12 #include "src/gpu/d3d/GrD3DUtil.h"
14 #include "include/gpu/d3d/GrD3DTypes.h"
17 GrD3DTexture::GrD3DTexture(GrD3DGpu* gpu, in GrD3DTexture() argument
24 : GrSurface(gpu, dimensions, info.fProtected) in GrD3DTexture()
26 , INHERITED(gpu, dimensions, info.fProtected, GrTextureType::k2D, mipmapStatus) in GrD3DTexture()
35 GrD3DTexture::GrD3DTexture(GrD3DGpu* gpu, SkISize dimensions, const GrD3DTextureResourceInfo& info, in GrD3DTexture() argument
40 : GrSurface(gpu, dimension in GrD3DTexture()
52 GrD3DTexture(GrD3DGpu* gpu, SkISize dimensions, const GrD3DTextureResourceInfo& info, sk_sp<GrD3DResourceState> state, const GrD3DDescriptorHeap::CPUHandle& shaderResourceView, GrMipmapStatus mipmapStatus) GrD3DTexture() argument
65 MakeNewTexture(GrD3DGpu* gpu, SkBudgeted budgeted, SkISize dimensions, const D3D12_RESOURCE_DESC& desc, GrProtected isProtected, GrMipmapStatus mipmapStatus) MakeNewTexture() argument
89 MakeWrappedTexture(GrD3DGpu* gpu, SkISize dimensions, GrWrapCacheable cacheable, GrIOType ioType, const GrD3DTextureResourceInfo& info, sk_sp<GrD3DResourceState> state) MakeWrappedTexture() argument
111 MakeAliasingTexture(GrD3DGpu* gpu, sk_sp<GrD3DTexture> originalTexture, const D3D12_RESOURCE_DESC& newDesc, D3D12_RESOURCE_STATES resourceState) MakeAliasingTexture() argument
136 GrD3DGpu* gpu = this->getD3DGpu(); onRelease() local
144 GrD3DGpu* gpu = this->getD3DGpu(); onAbandon() local
[all...]
/third_party/libdrm/etnaviv/
H A Detnaviv_gpu.c49 struct etna_gpu *gpu; in etna_gpu_new() local
51 gpu = calloc(1, sizeof(*gpu)); in etna_gpu_new()
52 if (!gpu) { in etna_gpu_new()
57 gpu->dev = dev; in etna_gpu_new()
58 gpu->core = core; in etna_gpu_new()
60 gpu->model = get_param(dev, core, ETNAVIV_PARAM_GPU_MODEL); in etna_gpu_new()
61 gpu->revision = get_param(dev, core, ETNAVIV_PARAM_GPU_REVISION); in etna_gpu_new()
63 if (!gpu->model) in etna_gpu_new()
66 INFO_MSG(" GPU model: 0x%x (rev %x)", gpu in etna_gpu_new()
76 etna_gpu_del(struct etna_gpu *gpu) etna_gpu_del() argument
81 etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param, uint64_t *value) etna_gpu_get_param() argument
[all...]
/third_party/mesa3d/src/etnaviv/drm/
H A Detnaviv_gpu.c49 struct etna_gpu *gpu; in etna_gpu_new() local
51 gpu = calloc(1, sizeof(*gpu)); in etna_gpu_new()
52 if (!gpu) { in etna_gpu_new()
57 gpu->dev = dev; in etna_gpu_new()
58 gpu->core = core; in etna_gpu_new()
60 gpu->model = get_param(dev, core, ETNAVIV_PARAM_GPU_MODEL); in etna_gpu_new()
61 gpu->revision = get_param(dev, core, ETNAVIV_PARAM_GPU_REVISION); in etna_gpu_new()
63 if (!gpu->model) in etna_gpu_new()
66 DEBUG_MSG(" GPU model: 0x%x (rev %x)", gpu in etna_gpu_new()
76 etna_gpu_del(struct etna_gpu *gpu) etna_gpu_del() argument
81 etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param, uint64_t *value) etna_gpu_get_param() argument
[all...]

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