Lines Matching refs:gpu
90 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
95 lockdep_assert_held(&gpu->lock);
103 if (gpu->exec_state == ETNA_PIPE_2D)
105 else if (gpu->exec_state == ETNA_PIPE_3D)
116 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
122 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
124 &gpu->mmu_context->cmdbuf_mapping) +
152 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
159 &gpu->mmu_context->cmdbuf_mapping) +
163 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
165 struct etnaviv_cmdbuf *buffer = &gpu->buffer;
167 lockdep_assert_held(&gpu->lock);
172 CMD_WAIT(buffer, gpu->fe_waitcycles);
174 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
180 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
182 struct etnaviv_cmdbuf *buffer = &gpu->buffer;
184 lockdep_assert_held(&gpu->lock);
188 if (gpu->identity.features & chipFeatures_PIPE_3D) {
198 if (gpu->identity.features & chipFeatures_PIPE_2D) {
215 u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)
217 struct etnaviv_cmdbuf *buffer = &gpu->buffer;
219 lockdep_assert_held(&gpu->lock);
233 void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
235 struct etnaviv_cmdbuf *buffer = &gpu->buffer;
238 bool has_blt = !!(gpu->identity.minor_features5 &
241 lockdep_assert_held(&gpu->lock);
243 if (gpu->exec_state == ETNA_PIPE_2D)
245 else if (gpu->exec_state == ETNA_PIPE_3D)
258 link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
269 if (gpu->exec_state == ETNA_PIPE_3D) {
301 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
303 struct etnaviv_cmdbuf *buffer = &gpu->buffer;
307 lockdep_assert_held(&gpu->lock);
314 target = etnaviv_buffer_reserve(gpu, buffer, dwords);
324 CMD_WAIT(buffer, gpu->fe_waitcycles);
326 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
340 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
344 struct etnaviv_cmdbuf *buffer = &gpu->buffer;
348 bool switch_context = gpu->exec_state != exec_state;
349 bool switch_mmu_context = gpu->mmu_context != mmu_context;
350 unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
351 bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
352 bool has_blt = !!(gpu->identity.minor_features5 &
355 lockdep_assert_held(&gpu->lock);
358 etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
361 &gpu->mmu_context->cmdbuf_mapping);
377 if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)
388 if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)
391 target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
399 struct etnaviv_iommu_context *old_context = gpu->mmu_context;
401 gpu->mmu_context = etnaviv_iommu_context_get(mmu_context);
407 if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {
419 gpu->sec_mode == ETNA_SEC_KERNEL) {
421 etnaviv_iommuv2_get_pta_id(gpu->mmu_context);
427 if (gpu->sec_mode == ETNA_SEC_NONE)
428 flush |= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);
438 gpu->flush_seq = new_flush_seq;
442 etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
443 gpu->exec_state = exec_state;
448 &gpu->mmu_context->cmdbuf_mapping);
472 return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
479 if (gpu->exec_state == ETNA_PIPE_2D) {
507 CMD_WAIT(buffer, gpu->fe_waitcycles);
509 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
515 etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),
538 etnaviv_buffer_dump(gpu, buffer, 0, 0x50);