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Searched refs:base (Results 151 - 175 of 11946) sorted by relevance

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/kernel/linux/linux-5.10/drivers/scsi/
H A Dfdomain.c112 int base; member
120 outb(0, fd->base + REG_BCTL); in fdomain_make_bus_idle()
121 outb(0, fd->base + REG_MCTL); in fdomain_make_bus_idle()
125 fd->base + REG_ACTL); in fdomain_make_bus_idle()
127 outb(ACTL_RESET | PARITY_MASK, fd->base + REG_ACTL); in fdomain_make_bus_idle()
154 static int fdomain_test_loopback(int base) in fdomain_test_loopback() argument
159 outb(i, base + REG_LOOPBACK); in fdomain_test_loopback()
160 if (inb(base + REG_LOOPBACK) != i) in fdomain_test_loopback()
167 static void fdomain_reset(int base) in fdomain_reset() argument
169 outb(BCTL_RST, base in fdomain_reset()
504 fdomain_create(int base, int irq, int this_id, struct device *dev) fdomain_create() argument
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/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-vic.c51 * @irq: The IRQ number for the base of the VIC.
52 * @base: The register base for the VIC.
63 void __iomem *base; member
84 * @base: Base of the VIC.
89 static void vic_init2(void __iomem *base) in vic_init2() argument
94 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); in vic_init2()
98 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
104 void __iomem *base = vic->base; in resume_one_vic() local
134 void __iomem *base = vic->base; suspend_one_vic() local
268 vic_register(void __iomem *base, unsigned int parent_irq, unsigned int irq, u32 valid_sources, u32 resume_sources, struct device_node *node) vic_register() argument
308 void __iomem *base = irq_data_get_irq_chip_data(d); vic_ack_irq() local
317 void __iomem *base = irq_data_get_irq_chip_data(d); vic_mask_irq() local
324 void __iomem *base = irq_data_get_irq_chip_data(d); vic_unmask_irq() local
375 vic_disable(void __iomem *base) vic_disable() argument
384 vic_clear_interrupts(void __iomem *base) vic_clear_interrupts() argument
404 vic_init_st(void __iomem *base, unsigned int irq_start, u32 vic_sources, struct device_node *node) vic_init_st() argument
434 __vic_init(void __iomem *base, int parent_irq, int irq_start, u32 vic_sources, u32 resume_sources, struct device_node *node) __vic_init() argument
481 vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources) vic_init() argument
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/kernel/linux/linux-6.6/drivers/scsi/
H A Dfdomain.c112 int base; member
125 outb(0, fd->base + REG_BCTL); in fdomain_make_bus_idle()
126 outb(0, fd->base + REG_MCTL); in fdomain_make_bus_idle()
130 fd->base + REG_ACTL); in fdomain_make_bus_idle()
132 outb(ACTL_RESET | PARITY_MASK, fd->base + REG_ACTL); in fdomain_make_bus_idle()
159 static int fdomain_test_loopback(int base) in fdomain_test_loopback() argument
164 outb(i, base + REG_LOOPBACK); in fdomain_test_loopback()
165 if (inb(base + REG_LOOPBACK) != i) in fdomain_test_loopback()
172 static void fdomain_reset(int base) in fdomain_reset() argument
174 outb(BCTL_RST, base in fdomain_reset()
514 fdomain_create(int base, int irq, int this_id, struct device *dev) fdomain_create() argument
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/kernel/linux/linux-6.6/drivers/phy/samsung/
H A Dphy-exynos-pcie.c39 void __iomem *base; member
44 static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) in exynos_pcie_phy_writel() argument
46 writel(val, base + offset); in exynos_pcie_phy_writel()
73 exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3)); in exynos5433_pcie_phy_init()
76 exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20)); in exynos5433_pcie_phy_init()
77 exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b)); in exynos5433_pcie_phy_init()
80 exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4)); in exynos5433_pcie_phy_init()
81 exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7)); in exynos5433_pcie_phy_init()
82 exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21)); in exynos5433_pcie_phy_init()
83 exynos_pcie_phy_writel(ep->base, in exynos5433_pcie_phy_init()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.c39 enc10->base.ctx
41 enc10->base.ctx->logger
107 enc10->base.funcs = &dcn30_link_enc_funcs; in dcn30_link_encoder_construct()
108 enc10->base.ctx = init_data->ctx; in dcn30_link_encoder_construct()
109 enc10->base.id = init_data->encoder; in dcn30_link_encoder_construct()
111 enc10->base.hpd_source = init_data->hpd_source; in dcn30_link_encoder_construct()
112 enc10->base.connector = init_data->connector; in dcn30_link_encoder_construct()
114 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; in dcn30_link_encoder_construct()
116 enc10->base.features = *enc_features; in dcn30_link_encoder_construct()
118 enc10->base in dcn30_link_encoder_construct()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dio_link_encoder.c36 enc10->base.ctx
38 enc10->base.ctx->logger
93 enc10->base.funcs = &dcn301_link_enc_funcs; in dcn301_link_encoder_construct()
94 enc10->base.ctx = init_data->ctx; in dcn301_link_encoder_construct()
95 enc10->base.id = init_data->encoder; in dcn301_link_encoder_construct()
97 enc10->base.hpd_source = init_data->hpd_source; in dcn301_link_encoder_construct()
98 enc10->base.connector = init_data->connector; in dcn301_link_encoder_construct()
100 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; in dcn301_link_encoder_construct()
102 enc10->base.features = *enc_features; in dcn301_link_encoder_construct()
104 enc10->base in dcn301_link_encoder_construct()
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/kernel/linux/linux-6.6/kernel/time/
H A Dhrtimer.c65 * to reach a base using a clockid, hrtimer_clockid_to_base()
135 * timer->base->cpu_base
147 static inline bool is_migration_base(struct hrtimer_clock_base *base) in is_migration_base() argument
149 return base == &migration_base; in is_migration_base()
154 * means that all timers which are tied to this base via timer->base are
155 * locked, and the base itself is locked too.
160 * When the timer's base is locked, and the timer removed from list, it is
161 * possible to set timer->base = &migration_base and drop the lock: the timer
167 __acquires(&timer->base
169 struct hrtimer_clock_base *base; global() variable
203 get_target_base(struct hrtimer_cpu_base *base, int pinned) get_target_base() argument
226 switch_hrtimer_base(struct hrtimer *timer, struct hrtimer_clock_base *base, int pinned) switch_hrtimer_base() argument
277 is_migration_base(struct hrtimer_clock_base *base) is_migration_base() argument
286 struct hrtimer_clock_base *base = timer->base; global() variable
509 struct hrtimer_clock_base *base; __hrtimer_next_event_base() local
627 hrtimer_update_base(struct hrtimer_cpu_base *base) hrtimer_update_base() argument
739 struct hrtimer_cpu_base *base = this_cpu_ptr(&hrtimer_bases); hrtimer_switch_to_hres() local
775 struct hrtimer_cpu_base *base = this_cpu_ptr(&hrtimer_bases); retrigger_next_event() local
813 struct hrtimer_clock_base *base = timer->base; hrtimer_reprogram() local
874 struct hrtimer_clock_base *base; update_needs_ipi() local
1083 enqueue_hrtimer(struct hrtimer *timer, struct hrtimer_clock_base *base, enum hrtimer_mode mode) enqueue_hrtimer() argument
1108 __remove_hrtimer(struct hrtimer *timer, struct hrtimer_clock_base *base, u8 newstate, int reprogram) __remove_hrtimer() argument
1139 remove_hrtimer(struct hrtimer *timer, struct hrtimer_clock_base *base, bool restart, bool keep_local) remove_hrtimer() argument
1216 __hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim, u64 delta_ns, const enum hrtimer_mode mode, struct hrtimer_clock_base *base) __hrtimer_start_range_ns() argument
1287 struct hrtimer_clock_base *base; hrtimer_start_range_ns() local
1322 struct hrtimer_clock_base *base; hrtimer_try_to_cancel() local
1348 hrtimer_cpu_base_init_expiry_lock(struct hrtimer_cpu_base *base) hrtimer_cpu_base_init_expiry_lock() argument
1353 hrtimer_cpu_base_lock_expiry(struct hrtimer_cpu_base *base) hrtimer_cpu_base_lock_expiry() argument
1358 hrtimer_cpu_base_unlock_expiry(struct hrtimer_cpu_base *base) hrtimer_cpu_base_unlock_expiry() argument
1400 struct hrtimer_clock_base *base = READ_ONCE(timer->base); hrtimer_cancel_wait_running() local
1425 hrtimer_cpu_base_init_expiry_lock(struct hrtimer_cpu_base *base) hrtimer_cpu_base_init_expiry_lock() argument
1427 hrtimer_cpu_base_lock_expiry(struct hrtimer_cpu_base *base) hrtimer_cpu_base_lock_expiry() argument
1429 hrtimer_cpu_base_unlock_expiry(struct hrtimer_cpu_base *base) hrtimer_cpu_base_unlock_expiry() argument
1430 hrtimer_sync_wait_running(struct hrtimer_cpu_base *base, unsigned long flags) hrtimer_sync_wait_running() argument
1536 int base = hrtimer_clock_to_base_table[clock_id]; hrtimer_clockid_to_base() local
1550 int base; __hrtimer_init() local
1610 struct hrtimer_clock_base *base; hrtimer_active() local
1724 struct hrtimer_clock_base *base; __hrtimer_run_queues() local
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/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-goldfish.c16 void __iomem *base; member
32 void __iomem *base = timerdrv->base; in goldfish_timer_read() local
40 time_low = gf_ioread32(base + TIMER_TIME_LOW); in goldfish_timer_read()
41 time_high = gf_ioread32(base + TIMER_TIME_HIGH); in goldfish_timer_read()
51 void __iomem *base = timerdrv->base; in goldfish_timer_set_oneshot() local
53 gf_iowrite32(0, base + TIMER_ALARM_HIGH); in goldfish_timer_set_oneshot()
54 gf_iowrite32(0, base + TIMER_ALARM_LOW); in goldfish_timer_set_oneshot()
55 gf_iowrite32(1, base in goldfish_timer_set_oneshot()
63 void __iomem *base = timerdrv->base; goldfish_timer_shutdown() local
74 void __iomem *base = timerdrv->base; goldfish_timer_next_event() local
91 void __iomem *base = timerdrv->base; goldfish_timer_irq() local
100 goldfish_timer_init(int irq, void __iomem *base) goldfish_timer_init() argument
[all...]
H A Dtimer-lpc32xx.c42 void __iomem *base; member
75 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
76 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_next_event()
77 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
88 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_shutdown()
102 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_oneshot()
106 LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR); in lpc32xx_clkevt_oneshot()
117 ddata->base + LPC32XX_TIMER_MCR); in lpc32xx_clkevt_periodic()
123 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
124 writel_relaxed(ddata->ticks_per_jiffy, ddata->base in lpc32xx_clkevt_periodic()
157 void __iomem *base; lpc32xx_clocksource_init() local
218 void __iomem *base; lpc32xx_clockevent_init() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/
H A Ddrm_displayid.c13 const struct displayid_header *base; in displayid_get_header() local
15 if (sizeof(*base) > length - index) in displayid_get_header()
18 base = (const struct displayid_header *)&displayid[index]; in displayid_get_header()
20 return base; in displayid_get_header()
28 const struct displayid_header *base; in validate_displayid() local
30 base = displayid_get_header(displayid, length, idx); in validate_displayid()
31 if (IS_ERR(base)) in validate_displayid()
32 return base; in validate_displayid()
34 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", in validate_displayid()
35 base in validate_displayid()
57 const struct displayid_header *base; drm_find_displayid_extension() local
140 const struct displayid_header *base; __displayid_iter_next() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/vmwgfx/
H A Dttm_object.c73 * for fast lookup of ref objects given a base object.
118 * that way, one can easily detect whether a base object is referenced by
120 * multiple ref objects if a ttm_object_file references the same base
191 struct ttm_base_object *base, in ttm_base_object_init()
199 base->shareable = shareable; in ttm_base_object_init()
200 base->tfile = ttm_object_file_ref(tfile); in ttm_base_object_init()
201 base->refcount_release = refcount_release; in ttm_base_object_init()
202 base->object_type = object_type; in ttm_base_object_init()
203 kref_init(&base->refcount); in ttm_base_object_init()
206 ret = idr_alloc(&tdev->idr, base, in ttm_base_object_init()
190 ttm_base_object_init(struct ttm_object_file *tfile, struct ttm_base_object *base, bool shareable, enum ttm_object_type object_type, void (*refcount_release) (struct ttm_base_object **)) ttm_base_object_init() argument
229 struct ttm_base_object *base = ttm_release_base() local
250 struct ttm_base_object *base = *p_base; ttm_base_object_unref() local
260 struct ttm_base_object *base = NULL; ttm_base_object_lookup() local
281 struct ttm_base_object *base; ttm_base_object_lookup_for_ref() local
293 ttm_ref_object_add(struct ttm_object_file *tfile, struct ttm_base_object *base, bool *existed, bool require_existed) ttm_ref_object_add() argument
493 struct ttm_base_object *base = *p_base; ttm_prime_refcount_release() local
518 struct ttm_base_object *base = &prime->base; ttm_prime_dmabuf_release() local
547 struct ttm_base_object *base; ttm_prime_fd_to_handle() local
581 struct ttm_base_object *base; ttm_prime_handle_to_fd() local
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/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dpc873xx.c13 static unsigned int base, model; variable
18 return base; in pc873xx_get_base()
26 static unsigned char __init pc873xx_read(unsigned int base, int reg) in pc873xx_read() argument
28 outb(reg, base); in pc873xx_read()
29 return inb(base + 1); in pc873xx_read()
32 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) in pc873xx_write() argument
37 outb(reg, base); in pc873xx_write()
38 outb(data, base + 1); in pc873xx_write()
39 outb(data, base + 1); /* Must be written twice */ in pc873xx_write()
47 while ((base in pc873xx_probe()
[all...]
/kernel/linux/linux-6.6/arch/alpha/kernel/
H A Dpc873xx.c13 static unsigned int base, model; variable
18 return base; in pc873xx_get_base()
26 static unsigned char __init pc873xx_read(unsigned int base, int reg) in pc873xx_read() argument
28 outb(reg, base); in pc873xx_read()
29 return inb(base + 1); in pc873xx_read()
32 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) in pc873xx_write() argument
37 outb(reg, base); in pc873xx_write()
38 outb(data, base + 1); in pc873xx_write()
39 outb(data, base + 1); /* Must be written twice */ in pc873xx_write()
47 while ((base in pc873xx_probe()
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/kernel/linux/linux-5.10/drivers/ide/
H A Dpalm_bk3710.c64 static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, in palm_bk3710_setudmamode() argument
79 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
81 writel(val32, base + BK3710_UDMASTB); in palm_bk3710_setudmamode()
84 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
86 writel(val32, base + BK3710_UDMATRP); in palm_bk3710_setudmamode()
89 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
91 writel(val32, base + BK3710_UDMAENV); in palm_bk3710_setudmamode()
94 val16 = readw(base + BK3710_UDMACTL) | (1 << dev); in palm_bk3710_setudmamode()
95 writew(val16, base + BK3710_UDMACTL); in palm_bk3710_setudmamode()
98 static void palm_bk3710_setdmamode(void __iomem *base, unsigne argument
130 palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, unsigned int dev, unsigned int cycletime, unsigned int mode) palm_bk3710_setpiomode() argument
181 void __iomem *base = (void __iomem *)hwif->dma_base; palm_bk3710_set_dma_mode() local
199 void __iomem *base = (void __iomem *)hwif->dma_base; palm_bk3710_set_pio_mode() local
210 palm_bk3710_chipinit(void __iomem *base) palm_bk3710_chipinit() argument
304 void __iomem *base; palm_bk3710_probe() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
40 .base = { 0x01100, 0x01500, 0x01900 },
49 .base = { 0x01d00, 0x02100, 0x02500 },
57 .base = { 0x02900, 0x02d00 },
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
83 .base = { 0x04500, 0x04900, 0x04d00 },
87 .base = { 0x21a00, 0x21b00, 0x21c00 },
90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
124 .base = { 0x00500, 0x00600 },
129 .base
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c185 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit() local
190 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, in dsi_pll_ssc_commit()
192 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, in dsi_pll_ssc_commit()
194 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, in dsi_pll_ssc_commit()
196 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, in dsi_pll_ssc_commit()
198 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, in dsi_pll_ssc_commit()
200 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, in dsi_pll_ssc_commit()
202 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
209 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg() local
211 dsi_phy_write(base in dsi_pll_config_hzindep_reg()
238 void __iomem *base = pll->phy->pll_base; dsi_pll_commit() local
424 void __iomem *base = pll_10nm->phy->pll_base; dsi_pll_10nm_vco_recalc_rate() local
545 void __iomem *base = phy->base; dsi_10nm_set_usecase() local
724 void __iomem *base = phy->base; dsi_phy_hw_v3_0_is_pll_on() local
810 void __iomem *base = phy->base; dsi_10nm_phy_enable() local
912 void __iomem *base = phy->base; dsi_10nm_phy_disable() local
[all...]
H A Ddsi_phy_7nm.c192 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit() local
197 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, in dsi_pll_ssc_commit()
199 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, in dsi_pll_ssc_commit()
201 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, in dsi_pll_ssc_commit()
203 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, in dsi_pll_ssc_commit()
205 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, in dsi_pll_ssc_commit()
207 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, in dsi_pll_ssc_commit()
209 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
216 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg() local
245 dsi_phy_write(base in dsi_pll_config_hzindep_reg()
280 void __iomem *base = pll->phy->pll_base; dsi_pll_commit() local
473 void __iomem *base = pll_7nm->phy->pll_base; dsi_pll_7nm_vco_recalc_rate() local
594 void __iomem *base = phy->base; dsi_7nm_set_usecase() local
792 void __iomem *base = phy->base; dsi_phy_hw_v4_0_is_pll_on() local
859 void __iomem *base = phy->base; dsi_7nm_phy_enable() local
1067 void __iomem *base = phy->base; dsi_7nm_set_continuous_clock() local
1082 void __iomem *base = phy->base; dsi_7nm_phy_disable() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_layer.h11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \
12 ((base) + 0x30 * (layer) + 0x0)
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \
14 ((base) + 0x30 * (layer) + 0x4)
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \
16 ((base) + 0x30 * (layer) + 0x8)
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \
18 ((base) + 0x30 * (layer) + 0xc + 4 * (plane))
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \
20 ((base)
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H A Dsun8i_ui_scaler.h26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0)
27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40)
28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80)
29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88)
30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base)
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/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
H A Dsun8i_ui_scaler.h26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0)
27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40)
28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80)
29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88)
30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base)
[all...]
/kernel/linux/linux-5.10/drivers/misc/lkdtm/
H A Dheap.c32 int *base, *again; in lkdtm_WRITE_AFTER_FREE() local
39 size_t offset = (len / sizeof(*base)) / 2; in lkdtm_WRITE_AFTER_FREE()
41 base = kmalloc(len, GFP_KERNEL); in lkdtm_WRITE_AFTER_FREE()
42 if (!base) in lkdtm_WRITE_AFTER_FREE()
44 pr_info("Allocated memory %p-%p\n", base, &base[offset * 2]); in lkdtm_WRITE_AFTER_FREE()
46 &base[offset]); in lkdtm_WRITE_AFTER_FREE()
47 kfree(base); in lkdtm_WRITE_AFTER_FREE()
48 base[offset] = 0x0abcdef0; in lkdtm_WRITE_AFTER_FREE()
52 if (again != base) in lkdtm_WRITE_AFTER_FREE()
58 int *base, *val, saw; lkdtm_READ_AFTER_FREE() local
123 int *base; lkdtm_READ_BUDDY_AFTER_FREE() local
[all...]
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dcs35l56.c89 ret = pm_runtime_resume_and_get(cs35l56->base.dev); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
96 ret = regmap_bulk_read(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT, in cs35l56_sync_asp1_mixer_widgets_with_firmware()
99 pm_runtime_mark_last_busy(cs35l56->base.dev); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
100 pm_runtime_put_autosuspend(cs35l56->base.dev); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
103 dev_err(cs35l56->base.dev, "Failed to read ASP1 mixer regs: %d\n", ret); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
117 dev_warn(cs35l56->base.dev, "Could not find control %s\n", name); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
146 ret = regmap_read(cs35l56->base.regmap, addr, &val); in cs35l56_dspwait_asp1tx_get()
176 ret = regmap_update_bits_check(cs35l56->base.regmap, addr, in cs35l56_dspwait_asp1tx_put()
288 dev_dbg(cs35l56->base.dev, "play: %d\n", event); in cs35l56_play_event()
293 return regmap_write(cs35l56->base in cs35l56_play_event()
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-lpc32xx.c46 void __iomem *base; member
79 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
80 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_next_event()
81 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
92 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_shutdown()
106 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_oneshot()
110 LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR); in lpc32xx_clkevt_oneshot()
121 ddata->base + LPC32XX_TIMER_MCR); in lpc32xx_clkevt_periodic()
127 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
128 writel_relaxed(ddata->ticks_per_jiffy, ddata->base in lpc32xx_clkevt_periodic()
161 void __iomem *base; lpc32xx_clocksource_init() local
222 void __iomem *base; lpc32xx_clockevent_init() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.c38 enc10->base.ctx
40 enc10->base.ctx->logger
106 enc10->base.funcs = &dcn30_link_enc_funcs; in dcn30_link_encoder_construct()
107 enc10->base.ctx = init_data->ctx; in dcn30_link_encoder_construct()
108 enc10->base.id = init_data->encoder; in dcn30_link_encoder_construct()
110 enc10->base.hpd_source = init_data->hpd_source; in dcn30_link_encoder_construct()
111 enc10->base.connector = init_data->connector; in dcn30_link_encoder_construct()
113 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; in dcn30_link_encoder_construct()
115 enc10->base.features = *enc_features; in dcn30_link_encoder_construct()
117 enc10->base in dcn30_link_encoder_construct()
[all...]
/kernel/linux/linux-6.6/drivers/crypto/intel/keembay/
H A Dkeembay-ocs-hcu-core.c414 base); in kmb_ocs_hcu_do_one_request()
884 .base.init = kmb_ocs_hcu_init,
885 .base.update = kmb_ocs_hcu_update,
886 .base.final = kmb_ocs_hcu_final,
887 .base.finup = kmb_ocs_hcu_finup,
888 .base.digest = kmb_ocs_hcu_digest,
889 .base.export = kmb_ocs_hcu_export,
890 .base.import = kmb_ocs_hcu_import,
891 .base.halg = {
894 .base
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