Lines Matching refs:base
89 ret = pm_runtime_resume_and_get(cs35l56->base.dev);
96 ret = regmap_bulk_read(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT,
99 pm_runtime_mark_last_busy(cs35l56->base.dev);
100 pm_runtime_put_autosuspend(cs35l56->base.dev);
103 dev_err(cs35l56->base.dev, "Failed to read ASP1 mixer regs: %d\n", ret);
117 dev_warn(cs35l56->base.dev, "Could not find control %s\n", name);
146 ret = regmap_read(cs35l56->base.regmap, addr, &val);
176 ret = regmap_update_bits_check(cs35l56->base.regmap, addr,
288 dev_dbg(cs35l56->base.dev, "play: %d\n", event);
293 return regmap_write(cs35l56->base.regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
297 ret = regmap_read_poll_timeout(cs35l56->base.regmap,
303 dev_err(cs35l56->base.dev, "PS0 wait failed: %d\n", ret);
306 return cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_PAUSE);
424 dev_dbg(cs35l56->base.dev, "%s: %d\n", __func__, event);
434 dev_dbg(cs35l56->base.dev, "%s: %#x\n", __func__, fmt);
440 dev_err(cs35l56->base.dev, "Unsupported clock source mode\n");
454 dev_err(cs35l56->base.dev, "Unsupported DAI format\n");
471 dev_err(cs35l56->base.dev, "Invalid clock invert\n");
475 regmap_update_bits(cs35l56->base.regmap,
482 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL3,
511 dev_dbg(cs35l56->base.dev, "tdm config cleared\n");
518 dev_err(cs35l56->base.dev, "tdm invalid slot width %d\n", slot_width);
524 dev_err(cs35l56->base.dev, "tdm invalid slot count %d\n", slots);
539 regmap_write(cs35l56->base.regmap, CS35L56_ASP1_FRAME_CONTROL1,
541 regmap_write(cs35l56->base.regmap, CS35L56_ASP1_FRAME_CONTROL5,
544 dev_dbg(cs35l56->base.dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n",
564 dev_dbg(cs35l56->base.dev, "%s: wl=%d, width=%d, rate=%d",
583 dev_err(cs35l56->base.dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq);
587 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1,
593 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2,
596 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL5,
599 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2,
602 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL1,
624 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1,
667 dev_dbg(cs35l56->base.dev, "%s: rate %d\n", __func__, params_rate(params));
669 if (!cs35l56->base.init_done)
789 dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret);
791 cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_REINIT);
799 ret = regmap_read(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS, &firmware_missing);
801 dev_err(cs35l56->base.dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
821 ret = cs35l56_firmware_shutdown(&cs35l56->base);
832 dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret);
836 mutex_lock(&cs35l56->base.irq_lock);
841 cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral);
851 dev_err(cs35l56->base.dev, "%s: init_completion timed out (SDW)\n",
859 regmap_clear_bits(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS,
861 cs35l56->base.fw_patched = true;
864 mutex_unlock(&cs35l56->base.irq_lock);
880 if (!cs35l56->base.init_done)
883 pm_runtime_get_sync(cs35l56->base.dev);
888 cs35l56->base.rev,
889 cs35l56->base.secured ? "-s" : "");
894 dev_dbg(cs35l56->base.dev, "DSP fwf name: '%s' system name: '%s'\n",
903 if (cs35l56->base.secured)
909 pm_runtime_mark_last_busy(cs35l56->base.dev);
910 pm_runtime_put_autosuspend(cs35l56->base.dev);
923 cs35l56->dsp.system_name = devm_kasprintf(cs35l56->base.dev,
933 dev_err(cs35l56->base.dev, "%s: init_completion timed out\n", __func__);
940 debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->base.init_done);
941 debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->base.can_hibernate);
942 debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->base.fw_patched);
948 regcache_drop_region(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT, CS35L56_ASP1TX4_INPUT);
1015 return cs35l56_runtime_suspend_common(&cs35l56->base);
1022 return cs35l56_runtime_resume_common(&cs35l56->base, false);
1040 if (cs35l56->base.irq)
1041 disable_irq(cs35l56->base.irq);
1058 if (cs35l56->base.reset_gpio) {
1059 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
1076 if (cs35l56->base.irq)
1077 enable_irq(cs35l56->base.irq);
1096 if (cs35l56->base.irq)
1097 disable_irq(cs35l56->base.irq);
1111 if (cs35l56->base.reset_gpio) {
1112 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
1124 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1);
1145 if (cs35l56->base.irq)
1146 enable_irq(cs35l56->base.irq);
1155 ret = cs35l56_is_fw_reload_needed(&cs35l56->base);
1156 dev_dbg(cs35l56->base.dev, "fw_reload_needed: %d\n", ret);
1160 cs35l56->base.fw_patched = false;
1185 cs35l56_init_cs_dsp(&cs35l56->base, &dsp->cs_dsp);
1190 dev_dbg(cs35l56->base.dev, "DSP system name: '%s'\n", dsp->system_name);
1194 dev_err(cs35l56->base.dev, "wm_halo_init failed\n");
1203 struct device *dev = cs35l56->base.dev;
1226 mutex_init(&cs35l56->base.irq_lock);
1228 dev_set_drvdata(cs35l56->base.dev, cs35l56);
1231 ret = devm_regulator_bulk_get(cs35l56->base.dev, ARRAY_SIZE(cs35l56->supplies),
1234 return dev_err_probe(cs35l56->base.dev, ret, "Failed to request supplies\n");
1237 cs35l56->base.reset_gpio = devm_gpiod_get_optional(cs35l56->base.dev, "reset",
1239 if (IS_ERR(cs35l56->base.reset_gpio)) {
1240 ret = PTR_ERR(cs35l56->base.reset_gpio);
1246 return dev_err_probe(cs35l56->base.dev, ret, "Failed to get reset GPIO\n");
1248 dev_info(cs35l56->base.dev, "Reset GPIO busy, assume shared reset\n");
1249 cs35l56->base.reset_gpio = NULL;
1254 return dev_err_probe(cs35l56->base.dev, ret, "Failed to enable supplies\n");
1256 if (cs35l56->base.reset_gpio) {
1258 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
1260 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1);
1269 dev_err_probe(cs35l56->base.dev, ret, "DSP init failed\n");
1273 ret = devm_snd_soc_register_component(cs35l56->base.dev,
1277 dev_err_probe(cs35l56->base.dev, ret, "Register codec failed\n");
1284 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
1302 if (cs35l56->base.init_done)
1305 pm_runtime_set_autosuspend_delay(cs35l56->base.dev, 100);
1306 pm_runtime_use_autosuspend(cs35l56->base.dev);
1307 pm_runtime_set_active(cs35l56->base.dev);
1308 pm_runtime_enable(cs35l56->base.dev);
1310 ret = cs35l56_hw_init(&cs35l56->base);
1314 ret = cs35l56_set_patch(&cs35l56->base);
1318 if (!cs35l56->base.reset_gpio) {
1319 dev_dbg(cs35l56->base.dev, "No reset gpio: using soft reset\n");
1321 cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral);
1324 pm_runtime_get_noresume(cs35l56->base.dev);
1334 if (cs35l56->sdw_peripheral && !cs35l56->base.init_done)
1335 pm_runtime_put_noidle(cs35l56->base.dev);
1337 regcache_mark_dirty(cs35l56->base.regmap);
1338 ret = cs35l56_wait_for_firmware_boot(&cs35l56->base);
1342 dev_dbg(cs35l56->base.dev, "Firmware rebooted after soft reset\n");
1346 ret = cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
1351 regcache_sync(cs35l56->base.regmap);
1354 ret = regmap_set_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL3,
1357 return dev_err_probe(cs35l56->base.dev, ret, "Failed to write ASP1_CONTROL3\n");
1359 cs35l56->base.init_done = true;
1368 cs35l56->base.init_done = false;
1374 if (cs35l56->base.irq)
1375 devm_free_irq(cs35l56->base.dev, cs35l56->base.irq, &cs35l56->base);
1380 pm_runtime_dont_use_autosuspend(cs35l56->base.dev);
1381 pm_runtime_suspend(cs35l56->base.dev);
1382 pm_runtime_disable(cs35l56->base.dev);
1384 regcache_cache_only(cs35l56->base.regmap, true);
1386 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);