Lines Matching refs:base
51 * @irq: The IRQ number for the base of the VIC.
52 * @base: The register base for the VIC.
63 void __iomem *base;
84 * @base: Base of the VIC.
89 static void vic_init2(void __iomem *base)
94 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
98 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
104 void __iomem *base = vic->base;
106 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
109 vic_init2(base);
111 writel(vic->int_select, base + VIC_INT_SELECT);
112 writel(vic->protect, base + VIC_PROTECT);
115 writel(vic->int_enable, base + VIC_INT_ENABLE);
116 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
120 writel(vic->soft_int, base + VIC_INT_SOFT);
121 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
134 void __iomem *base = vic->base;
136 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
138 vic->int_select = readl(base + VIC_INT_SELECT);
139 vic->int_enable = readl(base + VIC_INT_ENABLE);
140 vic->soft_int = readl(base + VIC_INT_SOFT);
141 vic->protect = readl(base + VIC_PROTECT);
146 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
147 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
193 irq_set_chip_data(irq, v->base);
209 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
226 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
255 * @base: The base address of the VIC.
257 * @irq: The base IRQ for the VIC.
268 static void __init vic_register(void __iomem *base, unsigned int parent_irq,
282 v->base = base;
299 /* If no base IRQ was passed, figure out our allocated base */
308 void __iomem *base = irq_data_get_irq_chip_data(d);
310 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
312 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
317 void __iomem *base = irq_data_get_irq_chip_data(d);
319 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
324 void __iomem *base = irq_data_get_irq_chip_data(d);
326 writel(1 << irq, base + VIC_INT_ENABLE);
375 static void __init vic_disable(void __iomem *base)
377 writel(0, base + VIC_INT_SELECT);
378 writel(0, base + VIC_INT_ENABLE);
379 writel(~0, base + VIC_INT_ENABLE_CLEAR);
380 writel(0, base + VIC_ITCR);
381 writel(~0, base + VIC_INT_SOFT_CLEAR);
384 static void __init vic_clear_interrupts(void __iomem *base)
388 writel(0, base + VIC_PL190_VECT_ADDR);
392 value = readl(base + VIC_PL190_VECT_ADDR);
393 writel(value, base + VIC_PL190_VECT_ADDR);
401 * the probe function is called twice, with base set to offset 000
404 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
408 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
411 vic_disable(base);
417 * the second base address, which is 0x20 in the page
420 vic_clear_interrupts(base);
424 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
428 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
431 vic_register(base, 0, irq_start, vic_sources, 0, node);
434 static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
445 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
450 base, cellid, vendor);
454 vic_init_st(base, irq_start, vic_sources, node);
464 vic_disable(base);
467 vic_clear_interrupts(base);
469 vic_init2(base);
471 vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
476 * @base: iomem base address
481 void __init vic_init(void __iomem *base, unsigned int irq_start,
484 __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);