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Searched refs:socfpgaclk (Results 1 - 18 of 18) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/socfpga/
H A Dclk-gate-s10.c17 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local
20 if (socfpgaclk->fixed_div) { in socfpga_gate_clk_recalc_rate()
21 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
22 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
23 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
24 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
33 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_dbg_clk_recalc_rate() local
36 val = readl(socfpgaclk->div_reg) >> socfpgaclk in socfpga_dbg_clk_recalc_rate()
46 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); socfpga_gate_get_parent() local
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H A Dclk-periph-s10.c21 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_c_clk_recalc_rate() local
25 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()
35 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_cnt_clk_recalc_rate() local
38 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()
39 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()
41 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()
42 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_peri_cnt_clk_recalc_rate()
50 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_periclk_get_parent() local
55 if (socfpgaclk->bypass_reg) { in clk_periclk_get_parent()
56 mask = (0x1 << socfpgaclk in clk_periclk_get_parent()
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H A Dclk-gate-a10.c24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local
27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local
45 if (socfpgaclk->clk_phase[0] || socfpgaclk in socfpga_clk_prepare()
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H A Dclk-pll-s10.c37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in agilex_clk_pll_recalc_rate() local
42 reg = readl(socfpgaclk->hw.reg); in agilex_clk_pll_recalc_rate()
48 reg = readl(socfpgaclk->hw.reg + 0x24); in agilex_clk_pll_recalc_rate()
58 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
65 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
72 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
82 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_boot_clk_recalc_rate() local
85 div = ((readl(socfpgaclk->hw.reg) & in clk_boot_clk_recalc_rate()
95 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
98 pll_src = readl(socfpgaclk in clk_pll_get_parent()
105 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); clk_boot_get_parent() local
115 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); clk_pll_prepare() local
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H A Dclk-periph-a10.c23 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local
26 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
27 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
30 div &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
33 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_periclk_recalc_rate()
41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_get_parent() local
45 clk_src = readl(socfpgaclk in clk_periclk_get_parent()
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H A Dclk-gate.c93 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local
96 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()
97 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()
98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
100 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_recalc_rate()
102 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
113 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local
119 if (socfpgaclk in socfpga_clk_prepare()
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H A Dclk-periph.c20 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local
23 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
24 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
28 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
31 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
H A Dclk-pll.c41 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
61 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
H A Dclk-pll-a10.c37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
/kernel/linux/linux-6.6/drivers/clk/socfpga/
H A Dclk-gate-s10.c24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local
27 if (socfpgaclk->fixed_div) { in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_dbg_clk_recalc_rate() local
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk in socfpga_dbg_clk_recalc_rate()
53 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); socfpga_gate_get_parent() local
83 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); socfpga_agilex_gate_get_parent() local
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H A Dclk-periph-s10.c21 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in n5x_clk_peri_c_clk_recalc_rate() local
23 unsigned long shift = socfpgaclk->shift; in n5x_clk_peri_c_clk_recalc_rate()
26 val = readl(socfpgaclk->hw.reg); in n5x_clk_peri_c_clk_recalc_rate()
36 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_c_clk_recalc_rate() local
40 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()
50 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_cnt_clk_recalc_rate() local
53 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()
54 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()
56 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()
57 div = ((readl(socfpgaclk in clk_peri_cnt_clk_recalc_rate()
65 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); clk_periclk_get_parent() local
[all...]
H A Dclk-pll-s10.c43 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in n5x_clk_pll_recalc_rate() local
48 reg = readl(socfpgaclk->hw.reg + 0x8); in n5x_clk_pll_recalc_rate()
64 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in agilex_clk_pll_recalc_rate() local
69 reg = readl(socfpgaclk->hw.reg); in agilex_clk_pll_recalc_rate()
75 reg = readl(socfpgaclk->hw.reg + 0x24); in agilex_clk_pll_recalc_rate()
85 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
92 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
99 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
109 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_boot_clk_recalc_rate() local
112 div = ((readl(socfpgaclk in clk_boot_clk_recalc_rate()
122 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); clk_pll_get_parent() local
132 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); clk_boot_get_parent() local
142 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); clk_pll_prepare() local
155 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); n5x_clk_pll_prepare() local
[all...]
H A Dclk-periph-a10.c23 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local
26 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
27 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
30 div &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
33 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_periclk_recalc_rate()
41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_get_parent() local
45 clk_src = readl(socfpgaclk in clk_periclk_get_parent()
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H A Dclk-gate.c90 static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk) in socfpga_clk_get_div() argument
94 if (socfpgaclk->fixed_div) in socfpga_clk_get_div()
95 div = socfpgaclk->fixed_div; in socfpga_clk_get_div()
96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()
98 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_get_div()
100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_get_div()
112 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local
113 u32 div = socfpga_clk_get_div(socfpgaclk); in socfpga_clk_recalc_rate()
122 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); socfpga_clk_determine_rate() local
[all...]
H A Dclk-periph.c20 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local
23 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
24 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
28 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
31 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
H A Dclk-gate-a10.c24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local
27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
H A Dclk-pll.c41 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
61 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
H A Dclk-pll-a10.c37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()

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