Lines Matching refs:socfpgaclk
24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
27 if (socfpgaclk->fixed_div)
28 div = socfpgaclk->fixed_div;
29 else if (socfpgaclk->div_reg) {
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
31 val &= GENMASK(socfpgaclk->width - 1, 0);
40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
47 switch (socfpgaclk->clk_phase[i]) {
79 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
80 regmap_write(socfpgaclk->sys_mgr_base_addr,