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Searched refs:post_div_shift (Results 1 - 25 of 54) sorted by relevance

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/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dclk-pll.h48 u8 post_div_shift; member
H A Dclk-alpha-pll.h82 * @post_div_shift: shift to differentiate between odd & even post-divider
94 int post_div_shift; member
H A Dmmcc-msm8998.c92 .post_div_shift = 8,
125 .post_div_shift = 8,
154 .post_div_shift = 8,
183 .post_div_shift = 8,
212 .post_div_shift = 8,
241 .post_div_shift = 8,
270 .post_div_shift = 8,
299 .post_div_shift = 8,
H A Dcamcc-sdm845.c68 .post_div_shift = 8,
96 .post_div_shift = 8,
124 .post_div_shift = 8,
152 .post_div_shift = 8,
H A Dclk-pll.c104 config >>= pll->post_div_shift; in clk_pll_recalc_rate()
H A Dlpasscorecc-sc7180.c88 .post_div_shift = 12,
H A Dgpucc-msm8998.c74 .post_div_shift = 8,
H A Dclk-alpha-pll.c1262 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1284 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1370 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1371 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dclk-pll.h48 u8 post_div_shift; member
H A Dcamcc-sc7280.c84 .post_div_shift = 8,
107 .post_div_shift = 12,
159 .post_div_shift = 8,
209 .post_div_shift = 8,
232 .post_div_shift = 8,
284 .post_div_shift = 8,
336 .post_div_shift = 8,
388 .post_div_shift = 8,
440 .post_div_shift = 8,
463 .post_div_shift
[all...]
H A Dlpassaudiocc-sc7280.c104 .post_div_shift = 8,
159 .post_div_shift = 8,
181 .post_div_shift = 12,
H A Dclk-alpha-pll.h98 * @post_div_shift: shift to differentiate between odd & even post-divider
110 int post_div_shift; member
H A Dgcc-sm6115.c83 .post_div_shift = 8,
103 .post_div_shift = 8,
153 .post_div_shift = 8,
207 .post_div_shift = 8,
266 .post_div_shift = 8,
305 .post_div_shift = 8,
344 .post_div_shift = 8,
401 .post_div_shift = 8,
453 .post_div_shift = 8,
H A Dcamcc-sm8450.c91 .post_div_shift = 10,
114 .post_div_shift = 14,
162 .post_div_shift = 10,
233 .post_div_shift = 10,
281 .post_div_shift = 10,
329 .post_div_shift = 10,
377 .post_div_shift = 10,
425 .post_div_shift = 10,
473 .post_div_shift = 10,
H A Dgpucc-sm6115.c89 .post_div_shift = 8,
144 .post_div_shift = 15,
H A Dmmcc-msm8998.c75 .post_div_shift = 8,
107 .post_div_shift = 8,
135 .post_div_shift = 8,
163 .post_div_shift = 8,
191 .post_div_shift = 8,
219 .post_div_shift = 8,
247 .post_div_shift = 8,
275 .post_div_shift = 8,
H A Dcamcc-sdm845.c51 .post_div_shift = 8,
83 .post_div_shift = 8,
115 .post_div_shift = 8,
147 .post_div_shift = 8,
H A Dcamcc-sm8250.c78 .post_div_shift = 8,
101 .post_div_shift = 12,
152 .post_div_shift = 8,
203 .post_div_shift = 8,
254 .post_div_shift = 8,
305 .post_div_shift = 8,
H A Dclk-alpha-pll.c1420 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1442 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1528 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1529 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1904 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1906 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
H A Dclk-pll.c104 config >>= pll->post_div_shift; in clk_pll_recalc_rate()
H A Dgpucc-msm8998.c79 .post_div_shift = 8,
H A Dlpasscorecc-sc7280.c72 .post_div_shift = 12,
H A Dgcc-qdu1000.c73 .post_div_shift = 10,
107 .post_div_shift = 10,
141 .post_div_shift = 10,
209 .post_div_shift = 10,
H A Dgcc-qcm2290.c81 .post_div_shift = 8,
198 .post_div_shift = 8,
269 .post_div_shift = 8,
342 .post_div_shift = 8,
394 .post_div_shift = 8,
H A Dgcc-sm6375.c85 .post_div_shift = 8,
107 .post_div_shift = 12,
227 .post_div_shift = 8,
300 .post_div_shift = 8,
371 .post_div_shift = 8,
423 .post_div_shift = 8,

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