18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci#ifndef __QCOM_CLK_ALPHA_PLL_H__ 58c2ecf20Sopenharmony_ci#define __QCOM_CLK_ALPHA_PLL_H__ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#include <linux/clk-provider.h> 88c2ecf20Sopenharmony_ci#include "clk-regmap.h" 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci/* Alpha PLL types */ 118c2ecf20Sopenharmony_cienum { 128c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_DEFAULT, 138c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_HUAYRA, 148c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_BRAMMO, 158c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_FABIA, 168c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_TRION, 178c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 188c2ecf20Sopenharmony_ci CLK_ALPHA_PLL_TYPE_MAX, 198c2ecf20Sopenharmony_ci}; 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_cienum { 228c2ecf20Sopenharmony_ci PLL_OFF_L_VAL, 238c2ecf20Sopenharmony_ci PLL_OFF_CAL_L_VAL, 248c2ecf20Sopenharmony_ci PLL_OFF_ALPHA_VAL, 258c2ecf20Sopenharmony_ci PLL_OFF_ALPHA_VAL_U, 268c2ecf20Sopenharmony_ci PLL_OFF_USER_CTL, 278c2ecf20Sopenharmony_ci PLL_OFF_USER_CTL_U, 288c2ecf20Sopenharmony_ci PLL_OFF_USER_CTL_U1, 298c2ecf20Sopenharmony_ci PLL_OFF_CONFIG_CTL, 308c2ecf20Sopenharmony_ci PLL_OFF_CONFIG_CTL_U, 318c2ecf20Sopenharmony_ci PLL_OFF_CONFIG_CTL_U1, 328c2ecf20Sopenharmony_ci PLL_OFF_TEST_CTL, 338c2ecf20Sopenharmony_ci PLL_OFF_TEST_CTL_U, 348c2ecf20Sopenharmony_ci PLL_OFF_TEST_CTL_U1, 358c2ecf20Sopenharmony_ci PLL_OFF_STATUS, 368c2ecf20Sopenharmony_ci PLL_OFF_OPMODE, 378c2ecf20Sopenharmony_ci PLL_OFF_FRAC, 388c2ecf20Sopenharmony_ci PLL_OFF_CAL_VAL, 398c2ecf20Sopenharmony_ci PLL_OFF_MAX_REGS 408c2ecf20Sopenharmony_ci}; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ciextern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_cistruct pll_vco { 458c2ecf20Sopenharmony_ci unsigned long min_freq; 468c2ecf20Sopenharmony_ci unsigned long max_freq; 478c2ecf20Sopenharmony_ci u32 val; 488c2ecf20Sopenharmony_ci}; 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#define VCO(a, b, c) { \ 518c2ecf20Sopenharmony_ci .val = a,\ 528c2ecf20Sopenharmony_ci .min_freq = b,\ 538c2ecf20Sopenharmony_ci .max_freq = c,\ 548c2ecf20Sopenharmony_ci} 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci/** 578c2ecf20Sopenharmony_ci * struct clk_alpha_pll - phase locked loop (PLL) 588c2ecf20Sopenharmony_ci * @offset: base address of registers 598c2ecf20Sopenharmony_ci * @vco_table: array of VCO settings 608c2ecf20Sopenharmony_ci * @regs: alpha pll register map (see @clk_alpha_pll_regs) 618c2ecf20Sopenharmony_ci * @clkr: regmap clock handle 628c2ecf20Sopenharmony_ci */ 638c2ecf20Sopenharmony_cistruct clk_alpha_pll { 648c2ecf20Sopenharmony_ci u32 offset; 658c2ecf20Sopenharmony_ci const u8 *regs; 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ci const struct pll_vco *vco_table; 688c2ecf20Sopenharmony_ci size_t num_vco; 698c2ecf20Sopenharmony_ci#define SUPPORTS_OFFLINE_REQ BIT(0) 708c2ecf20Sopenharmony_ci#define SUPPORTS_FSM_MODE BIT(2) 718c2ecf20Sopenharmony_ci#define SUPPORTS_DYNAMIC_UPDATE BIT(3) 728c2ecf20Sopenharmony_ci u8 flags; 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci struct clk_regmap clkr; 758c2ecf20Sopenharmony_ci}; 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_ci/** 788c2ecf20Sopenharmony_ci * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 798c2ecf20Sopenharmony_ci * @offset: base address of registers 808c2ecf20Sopenharmony_ci * @regs: alpha pll register map (see @clk_alpha_pll_regs) 818c2ecf20Sopenharmony_ci * @width: width of post-divider 828c2ecf20Sopenharmony_ci * @post_div_shift: shift to differentiate between odd & even post-divider 838c2ecf20Sopenharmony_ci * @post_div_table: table with PLL odd and even post-divider settings 848c2ecf20Sopenharmony_ci * @num_post_div: Number of PLL post-divider settings 858c2ecf20Sopenharmony_ci * 868c2ecf20Sopenharmony_ci * @clkr: regmap clock handle 878c2ecf20Sopenharmony_ci */ 888c2ecf20Sopenharmony_cistruct clk_alpha_pll_postdiv { 898c2ecf20Sopenharmony_ci u32 offset; 908c2ecf20Sopenharmony_ci u8 width; 918c2ecf20Sopenharmony_ci const u8 *regs; 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci struct clk_regmap clkr; 948c2ecf20Sopenharmony_ci int post_div_shift; 958c2ecf20Sopenharmony_ci const struct clk_div_table *post_div_table; 968c2ecf20Sopenharmony_ci size_t num_post_div; 978c2ecf20Sopenharmony_ci}; 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_cistruct alpha_pll_config { 1008c2ecf20Sopenharmony_ci u32 l; 1018c2ecf20Sopenharmony_ci u32 alpha; 1028c2ecf20Sopenharmony_ci u32 alpha_hi; 1038c2ecf20Sopenharmony_ci u32 config_ctl_val; 1048c2ecf20Sopenharmony_ci u32 config_ctl_hi_val; 1058c2ecf20Sopenharmony_ci u32 config_ctl_hi1_val; 1068c2ecf20Sopenharmony_ci u32 user_ctl_val; 1078c2ecf20Sopenharmony_ci u32 user_ctl_hi_val; 1088c2ecf20Sopenharmony_ci u32 user_ctl_hi1_val; 1098c2ecf20Sopenharmony_ci u32 test_ctl_val; 1108c2ecf20Sopenharmony_ci u32 test_ctl_hi_val; 1118c2ecf20Sopenharmony_ci u32 test_ctl_hi1_val; 1128c2ecf20Sopenharmony_ci u32 main_output_mask; 1138c2ecf20Sopenharmony_ci u32 aux_output_mask; 1148c2ecf20Sopenharmony_ci u32 aux2_output_mask; 1158c2ecf20Sopenharmony_ci u32 early_output_mask; 1168c2ecf20Sopenharmony_ci u32 alpha_en_mask; 1178c2ecf20Sopenharmony_ci u32 alpha_mode_mask; 1188c2ecf20Sopenharmony_ci u32 pre_div_val; 1198c2ecf20Sopenharmony_ci u32 pre_div_mask; 1208c2ecf20Sopenharmony_ci u32 post_div_val; 1218c2ecf20Sopenharmony_ci u32 post_div_mask; 1228c2ecf20Sopenharmony_ci u32 vco_val; 1238c2ecf20Sopenharmony_ci u32 vco_mask; 1248c2ecf20Sopenharmony_ci}; 1258c2ecf20Sopenharmony_ci 1268c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_ops; 1278c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_fixed_ops; 1288c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_hwfsm_ops; 1298c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_postdiv_ops; 1308c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_huayra_ops; 1318c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 1328c2ecf20Sopenharmony_ci 1338c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_fabia_ops; 1348c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 1358c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_trion_ops; 1388c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 1398c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 1408c2ecf20Sopenharmony_ci 1418c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_lucid_ops; 1428c2ecf20Sopenharmony_ci#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 1438c2ecf20Sopenharmony_ciextern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 1448c2ecf20Sopenharmony_ci 1458c2ecf20Sopenharmony_civoid clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1468c2ecf20Sopenharmony_ci const struct alpha_pll_config *config); 1478c2ecf20Sopenharmony_civoid clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1488c2ecf20Sopenharmony_ci const struct alpha_pll_config *config); 1498c2ecf20Sopenharmony_civoid clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1508c2ecf20Sopenharmony_ci const struct alpha_pll_config *config); 1518c2ecf20Sopenharmony_ci#define clk_lucid_pll_configure(pll, regmap, config) \ 1528c2ecf20Sopenharmony_ci clk_trion_pll_configure(pll, regmap, config) 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_ci 1558c2ecf20Sopenharmony_ci 1568c2ecf20Sopenharmony_ci#endif 157