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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c33 * @ih: ih ring to initialize
41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, in amdgpu_ih_ring_init() argument
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
52 ih->rptr = 0; in amdgpu_ih_ring_init()
53 ih->use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
58 if (ih->ring) in amdgpu_ih_ring_init()
64 ih in amdgpu_ih_ring_init()
116 amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) amdgpu_ih_ring_fini() argument
149 amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, const uint32_t *iv, unsigned int num_dw) amdgpu_ih_ring_write() argument
179 amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) amdgpu_ih_wait_on_checkpoint_process_ts() argument
208 amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) amdgpu_ih_process() argument
252 amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) amdgpu_ih_decode_iv_helper() argument
287 amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr, signed int offset) amdgpu_ih_decode_iv_ts_helper() argument
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H A Dvega10_ih.c41 * vega10_ih_init_register_offset - Initialize register offset for ih rings
45 * Initialize register offset ih rings (VEGA10).
51 if (adev->irq.ih.ring_size) { in vega10_ih_init_register_offset()
52 ih_regs = &adev->irq.ih.ih_regs; in vega10_ih_init_register_offset()
91 * @ih: amdgpu_ih_ring pointet
97 struct amdgpu_ih_ring *ih, in vega10_ih_toggle_ring_interrupts()
103 ih_regs = &ih->ih_regs; in vega10_ih_toggle_ring_interrupts()
109 if (ih == &adev->irq.ih) in vega10_ih_toggle_ring_interrupts()
121 ih in vega10_ih_toggle_ring_interrupts()
96 vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, bool enable) vega10_ih_toggle_ring_interrupts() argument
143 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; vega10_ih_toggle_interrupts() local
158 vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) vega10_ih_rb_cntl() argument
181 vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) vega10_ih_doorbell_rptr() argument
208 vega10_ih_enable_ring(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_enable_ring() argument
263 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; vega10_ih_irq_init() local
335 vega10_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_get_wptr() argument
393 vega10_ih_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_irq_rearm() argument
419 vega10_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_set_rptr() argument
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H A Dvega20_ih.c49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
53 * Initialize register offset ih rings (VEGA20).
59 if (adev->irq.ih.ring_size) { in vega20_ih_init_register_offset()
60 ih_regs = &adev->irq.ih.ih_regs; in vega20_ih_init_register_offset()
99 * @ih: amdgpu_ih_ring pointer
105 struct amdgpu_ih_ring *ih, in vega20_ih_toggle_ring_interrupts()
111 ih_regs = &ih->ih_regs; in vega20_ih_toggle_ring_interrupts()
118 if (ih == &adev->irq.ih) in vega20_ih_toggle_ring_interrupts()
130 ih in vega20_ih_toggle_ring_interrupts()
104 vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, bool enable) vega20_ih_toggle_ring_interrupts() argument
152 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; vega20_ih_toggle_interrupts() local
167 vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) vega20_ih_rb_cntl() argument
190 vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) vega20_ih_doorbell_rptr() argument
217 vega20_ih_enable_ring(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega20_ih_enable_ring() argument
282 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; vega20_ih_irq_init() local
383 vega20_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega20_ih_get_wptr() argument
441 vega20_ih_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega20_ih_irq_rearm() argument
468 vega20_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega20_ih_set_rptr() argument
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H A Dnavi10_ih.c43 * navi10_ih_init_register_offset - Initialize register offset for ih rings
47 * Initialize register offset ih rings (NAVI10).
53 if (adev->irq.ih.ring_size) { in navi10_ih_init_register_offset()
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
147 * @ih: amdgpu_ih_ring pointet
153 struct amdgpu_ih_ring *ih, in navi10_ih_toggle_ring_interrupts()
159 ih_regs = &ih->ih_regs; in navi10_ih_toggle_ring_interrupts()
165 if (ih == &adev->irq.ih) in navi10_ih_toggle_ring_interrupts()
176 ih in navi10_ih_toggle_ring_interrupts()
152 navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, bool enable) navi10_ih_toggle_ring_interrupts() argument
198 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; navi10_ih_toggle_interrupts() local
213 navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) navi10_ih_rb_cntl() argument
236 navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) navi10_ih_doorbell_rptr() argument
263 navi10_ih_enable_ring(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_enable_ring() argument
319 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; navi10_ih_irq_init() local
406 navi10_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_get_wptr() argument
462 navi10_ih_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_irq_rearm() argument
489 navi10_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_set_rptr() argument
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H A Dih_v6_0.c40 * ih_v6_0_init_register_offset - Initialize register offset for ih rings
44 * Initialize register offset ih rings (IH_V6_0).
50 /* ih ring 2 is removed in ih_v6_0_init_register_offset()
51 * ih ring and ih ring 1 are available */ in ih_v6_0_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
122 * @ih: amdgpu_ih_ring pointer
128 struct amdgpu_ih_ring *ih, in ih_v6_0_toggle_ring_interrupts()
134 ih_regs = &ih in ih_v6_0_toggle_ring_interrupts()
127 ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, bool enable) ih_v6_0_toggle_ring_interrupts() argument
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; ih_v6_0_toggle_interrupts() local
187 ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) ih_v6_0_rb_cntl() argument
210 ih_v6_0_doorbell_rptr(struct amdgpu_ih_ring *ih) ih_v6_0_doorbell_rptr() argument
237 ih_v6_0_enable_ring(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_0_enable_ring() argument
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; ih_v6_0_irq_init() local
391 ih_v6_0_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_0_get_wptr() argument
438 ih_v6_0_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_0_irq_rearm() argument
465 ih_v6_0_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_0_set_rptr() argument
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H A Dih_v6_1.c40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
44 * Initialize register offset ih rings (IH_V6_0).
50 /* ih ring 2 is removed in ih_v6_1_init_register_offset()
51 * ih ring and ih ring 1 are available */ in ih_v6_1_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
122 * @ih: amdgpu_ih_ring pointer
128 struct amdgpu_ih_ring *ih, in ih_v6_1_toggle_ring_interrupts()
134 ih_regs = &ih in ih_v6_1_toggle_ring_interrupts()
127 ih_v6_1_toggle_ring_interrupts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, bool enable) ih_v6_1_toggle_ring_interrupts() argument
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; ih_v6_1_toggle_interrupts() local
187 ih_v6_1_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) ih_v6_1_rb_cntl() argument
210 ih_v6_1_doorbell_rptr(struct amdgpu_ih_ring *ih) ih_v6_1_doorbell_rptr() argument
237 ih_v6_1_enable_ring(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_1_enable_ring() argument
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; ih_v6_1_irq_init() local
391 ih_v6_1_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_1_get_wptr() argument
439 ih_v6_1_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_1_irq_rearm() argument
466 ih_v6_1_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih_v6_1_set_rptr() argument
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H A Dtonga_ih.c67 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
87 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
105 struct amdgpu_ih_ring *ih = &adev->irq.ih; in tonga_ih_irq_init() local
123 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); in tonga_ih_irq_init()
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in tonga_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
146 if (adev->irq.ih in tonga_ih_irq_init()
192 tonga_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) tonga_ih_get_wptr() argument
242 tonga_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) tonga_ih_decode_iv() argument
274 tonga_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) tonga_ih_set_rptr() argument
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H A Damdgpu_ih.h81 /* provided by the ih block */
84 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
85 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
87 uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
89 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
92 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
94 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
95 #define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \
97 (adev)->irq.ih_funcs->decode_iv_ts((ih), (rpt
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H A Diceland_ih.c69 adev->irq.ih.enabled = true; in iceland_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in iceland_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in iceland_ih_irq_init() local
127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in iceland_ih_irq_init()
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in iceland_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
182 * @ih
190 iceland_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) iceland_ih_get_wptr() argument
238 iceland_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) iceland_ih_decode_iv() argument
270 iceland_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) iceland_ih_set_rptr() argument
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H A Dcik_ih.c69 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cik_ih_irq_init() local
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
180 * @ih
188 cik_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cik_ih_get_wptr() argument
248 cik_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) cik_ih_decode_iv() argument
280 cik_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cik_ih_set_rptr() argument
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H A Dcz_ih.c69 adev->irq.ih.enabled = true; in cz_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cz_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cz_ih_irq_init() local
127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cz_ih_irq_init()
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cz_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
182 * @ih
190 cz_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cz_ih_get_wptr() argument
239 cz_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) cz_ih_decode_iv() argument
271 cz_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cz_ih_set_rptr() argument
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H A Dsi_ih.c44 adev->irq.ih.enabled = true; in si_ih_enable_interrupts()
58 adev->irq.ih.enabled = false; in si_ih_disable_interrupts()
59 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
64 struct amdgpu_ih_ring *ih = &adev->irq.ih; in si_ih_irq_init() local
76 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
84 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
85 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in si_ih_irq_init()
108 struct amdgpu_ih_ring *ih) in si_ih_get_wptr()
107 si_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) si_ih_get_wptr() argument
132 si_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) si_ih_decode_iv() argument
153 si_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) si_ih_set_rptr() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c33 * @ih: ih ring to initialize
41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, in amdgpu_ih_ring_init() argument
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
52 ih->rptr = 0; in amdgpu_ih_ring_init()
53 ih->use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
58 if (ih->ring) in amdgpu_ih_ring_init()
64 ih in amdgpu_ih_ring_init()
114 amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) amdgpu_ih_ring_fini() argument
143 amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) amdgpu_ih_process() argument
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H A Dvega10_ih.c61 adev->irq.ih.enabled = true; in vega10_ih_enable_interrupts()
121 adev->irq.ih.enabled = false; in vega10_ih_disable_interrupts()
122 adev->irq.ih.rptr = 0; in vega10_ih_disable_interrupts()
166 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in vega10_ih_rb_cntl() argument
168 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl()
171 MC_SPACE, ih->use_bus_addr ? 1 : 4); in vega10_ih_rb_cntl()
189 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) in vega10_ih_doorbell_rptr() argument
193 if (ih->use_doorbell) { in vega10_ih_doorbell_rptr()
196 ih->doorbell_index); in vega10_ih_doorbell_rptr()
221 struct amdgpu_ih_ring *ih; in vega10_ih_irq_init() local
375 vega10_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_get_wptr() argument
437 vega10_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) vega10_ih_decode_iv() argument
478 vega10_ih_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_irq_rearm() argument
511 vega10_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) vega10_ih_set_rptr() argument
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H A Dnavi10_ih.c106 adev->irq.ih.enabled = true; in navi10_ih_enable_interrupts()
166 adev->irq.ih.enabled = false; in navi10_ih_disable_interrupts()
167 adev->irq.ih.rptr = 0; in navi10_ih_disable_interrupts()
211 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in navi10_ih_rb_cntl() argument
213 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl()
216 MC_SPACE, ih->use_bus_addr ? 1 : 4); in navi10_ih_rb_cntl()
234 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) in navi10_ih_doorbell_rptr() argument
238 if (ih->use_doorbell) { in navi10_ih_doorbell_rptr()
241 ih->doorbell_index); in navi10_ih_doorbell_rptr()
284 struct amdgpu_ih_ring *ih in navi10_ih_irq_init() local
449 navi10_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_get_wptr() argument
507 navi10_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) navi10_ih_decode_iv() argument
548 navi10_ih_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_irq_rearm() argument
581 navi10_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) navi10_ih_set_rptr() argument
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H A Dtonga_ih.c67 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
87 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
105 struct amdgpu_ih_ring *ih = &adev->irq.ih; in tonga_ih_irq_init() local
123 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); in tonga_ih_irq_init()
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in tonga_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
146 if (adev->irq.ih in tonga_ih_irq_init()
191 tonga_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) tonga_ih_get_wptr() argument
233 tonga_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) tonga_ih_decode_iv() argument
264 tonga_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) tonga_ih_set_rptr() argument
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H A Diceland_ih.c69 adev->irq.ih.enabled = true; in iceland_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in iceland_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in iceland_ih_irq_init() local
127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in iceland_ih_irq_init()
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in iceland_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
190 struct amdgpu_ih_ring *ih) in iceland_ih_get_wptr()
189 iceland_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) iceland_ih_get_wptr() argument
230 iceland_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) iceland_ih_decode_iv() argument
261 iceland_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) iceland_ih_set_rptr() argument
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H A Dcz_ih.c69 adev->irq.ih.enabled = true; in cz_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cz_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cz_ih_irq_init() local
127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cz_ih_irq_init()
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cz_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
190 struct amdgpu_ih_ring *ih) in cz_ih_get_wptr()
189 cz_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cz_ih_get_wptr() argument
231 cz_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) cz_ih_decode_iv() argument
262 cz_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cz_ih_set_rptr() argument
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H A Dcik_ih.c69 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cik_ih_irq_init() local
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
188 struct amdgpu_ih_ring *ih) in cik_ih_get_wptr()
187 cik_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cik_ih_get_wptr() argument
241 cik_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) cik_ih_decode_iv() argument
272 cik_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) cik_ih_set_rptr() argument
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H A Dsi_ih.c44 adev->irq.ih.enabled = true; in si_ih_enable_interrupts()
58 adev->irq.ih.enabled = false; in si_ih_disable_interrupts()
59 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
64 struct amdgpu_ih_ring *ih = &adev->irq.ih; in si_ih_irq_init() local
76 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
84 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
85 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in si_ih_irq_init()
108 struct amdgpu_ih_ring *ih) in si_ih_get_wptr()
107 si_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) si_ih_get_wptr() argument
126 si_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry) si_ih_decode_iv() argument
147 si_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) si_ih_set_rptr() argument
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H A Damdgpu_ih.h58 /* provided by the ih block */
61 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
62 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
64 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
67 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
69 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
70 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
72 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
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/kernel/linux/linux-5.10/fs/reiserfs/
H A Dlbalance.c26 struct item_head *ih; in leaf_copy_dir_entries() local
31 ih = item_head(source, item_num); in leaf_copy_dir_entries()
33 RFALSE(!is_direntry_le_ih(ih), "vs-10000: item must be directory item"); in leaf_copy_dir_entries()
39 deh = B_I_DEH(source, ih); in leaf_copy_dir_entries()
42 ih_item_len(ih)) - in leaf_copy_dir_entries()
45 source->b_data + ih_location(ih) + in leaf_copy_dir_entries()
63 (last_first == FIRST_TO_LAST && le_ih_k_offset(ih) == DOT_OFFSET) || in leaf_copy_dir_entries()
65 && comp_short_le_keys /*COMP_SHORT_KEYS */ (&ih->ih_key, in leaf_copy_dir_entries()
73 memcpy(&new_ih.ih_key, &ih->ih_key, KEY_SIZE); in leaf_copy_dir_entries()
82 if (from < ih_entry_count(ih)) { in leaf_copy_dir_entries()
141 struct item_head *ih; leaf_copy_boundary_item() local
191 "entirely (%h)", ih); leaf_copy_boundary_item() local
206 ih); leaf_copy_boundary_item() local
259 "vs-10050: items %h and %h do not match", ih, dih); leaf_copy_boundary_item() local
320 struct item_head *ih; leaf_copy_items_entirely() local
419 struct item_head *ih; leaf_item_bottle() local
868 struct item_head *ih; leaf_delete_items() local
909 struct item_head *ih; leaf_insert_into_buf() local
985 struct item_head *ih; leaf_paste_in_buffer() local
1072 leaf_cut_entries(struct buffer_head *bh, struct item_head *ih, int from, int del_count) leaf_cut_entries() argument
1151 struct item_head *ih; leaf_cut_from_buffer() local
1198 "10205: invalid ih_free_space (%h)", ih); leaf_cut_from_buffer() local
1248 struct item_head *ih; leaf_delete_items_entirely() local
1321 struct item_head *ih; leaf_paste_entries() local
1415 ih, deh + i - 1, i, deh + i); leaf_paste_entries() local
1421 ih, i, deh + i, deh + i + 1); leaf_paste_entries() local
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/kernel/linux/linux-6.6/fs/reiserfs/
H A Dlbalance.c26 struct item_head *ih; in leaf_copy_dir_entries() local
31 ih = item_head(source, item_num); in leaf_copy_dir_entries()
33 RFALSE(!is_direntry_le_ih(ih), "vs-10000: item must be directory item"); in leaf_copy_dir_entries()
39 deh = B_I_DEH(source, ih); in leaf_copy_dir_entries()
42 ih_item_len(ih)) - in leaf_copy_dir_entries()
45 source->b_data + ih_location(ih) + in leaf_copy_dir_entries()
63 (last_first == FIRST_TO_LAST && le_ih_k_offset(ih) == DOT_OFFSET) || in leaf_copy_dir_entries()
65 && comp_short_le_keys /*COMP_SHORT_KEYS */ (&ih->ih_key, in leaf_copy_dir_entries()
73 memcpy(&new_ih.ih_key, &ih->ih_key, KEY_SIZE); in leaf_copy_dir_entries()
82 if (from < ih_entry_count(ih)) { in leaf_copy_dir_entries()
141 struct item_head *ih; leaf_copy_boundary_item() local
191 "entirely (%h)", ih); leaf_copy_boundary_item() local
206 ih); leaf_copy_boundary_item() local
259 "vs-10050: items %h and %h do not match", ih, dih); leaf_copy_boundary_item() local
320 struct item_head *ih; leaf_copy_items_entirely() local
419 struct item_head *ih; leaf_item_bottle() local
868 struct item_head *ih; leaf_delete_items() local
909 struct item_head *ih; leaf_insert_into_buf() local
985 struct item_head *ih; leaf_paste_in_buffer() local
1072 leaf_cut_entries(struct buffer_head *bh, struct item_head *ih, int from, int del_count) leaf_cut_entries() argument
1151 struct item_head *ih; leaf_cut_from_buffer() local
1198 "10205: invalid ih_free_space (%h)", ih); leaf_cut_from_buffer() local
1248 struct item_head *ih; leaf_delete_items_entirely() local
1321 struct item_head *ih; leaf_paste_entries() local
1415 ih, deh + i - 1, i, deh + i); leaf_paste_entries() local
1421 ih, i, deh + i, deh + i + 1); leaf_paste_entries() local
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/kernel/linux/linux-5.10/net/ipv4/netfilter/
H A Dnf_log_ipv4.c40 const struct iphdr *ih; in dump_ipv4_packet() local
48 ih = skb_header_pointer(skb, iphoff, sizeof(_iph), &_iph); in dump_ipv4_packet()
49 if (ih == NULL) { in dump_ipv4_packet()
57 nf_log_buf_add(m, "SRC=%pI4 DST=%pI4 ", &ih->saddr, &ih->daddr); in dump_ipv4_packet()
61 ntohs(ih->tot_len), ih->tos & IPTOS_TOS_MASK, in dump_ipv4_packet()
62 ih->tos & IPTOS_PREC_MASK, ih->ttl, ntohs(ih in dump_ipv4_packet()
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/kernel/linux/linux-5.10/net/bridge/netfilter/
H A Debt_log.c99 const struct iphdr *ih; in ebt_log_packet() local
102 ih = skb_header_pointer(skb, 0, sizeof(_iph), &_iph); in ebt_log_packet()
103 if (ih == NULL) { in ebt_log_packet()
108 &ih->saddr, &ih->daddr, ih->tos, ih->protocol); in ebt_log_packet()
109 print_ports(skb, ih->protocol, ih->ihl*4); in ebt_log_packet()
116 const struct ipv6hdr *ih; in ebt_log_packet() local
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