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Searched refs:gpu (Results 1 - 25 of 169) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
H A Dmsm_gpu.c25 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail() argument
27 struct drm_device *dev = gpu->dev; in enable_pwrrail()
30 if (gpu->gpu_reg) { in enable_pwrrail()
31 ret = regulator_enable(gpu->gpu_reg); in enable_pwrrail()
38 if (gpu->gpu_cx) { in enable_pwrrail()
39 ret = regulator_enable(gpu->gpu_cx); in enable_pwrrail()
49 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail() argument
51 if (gpu->gpu_cx) in disable_pwrrail()
52 regulator_disable(gpu->gpu_cx); in disable_pwrrail()
53 if (gpu in disable_pwrrail()
58 enable_clk(struct msm_gpu *gpu) enable_clk() argument
70 disable_clk(struct msm_gpu *gpu) disable_clk() argument
88 enable_axi(struct msm_gpu *gpu) enable_axi() argument
93 disable_axi(struct msm_gpu *gpu) disable_axi() argument
99 msm_gpu_pm_resume(struct msm_gpu *gpu) msm_gpu_pm_resume() argument
125 msm_gpu_pm_suspend(struct msm_gpu *gpu) msm_gpu_pm_suspend() argument
151 msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx, struct drm_printer *p) msm_gpu_show_fdinfo() argument
159 msm_gpu_hw_init(struct msm_gpu *gpu) msm_gpu_hw_init() argument
181 struct msm_gpu *gpu = data; msm_gpu_devcoredump_read() local
216 struct msm_gpu *gpu = data; msm_gpu_devcoredump_free() local
257 msm_gpu_crashstate_capture(struct msm_gpu *gpu, struct msm_gem_submit *submit, char *comm, char *cmd) msm_gpu_crashstate_capture() argument
300 msm_gpu_crashstate_capture(struct msm_gpu *gpu, struct msm_gem_submit *submit, char *comm, char *cmd) msm_gpu_crashstate_capture() argument
356 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); recover_worker() local
451 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work); fault_worker() local
487 hangcheck_timer_reset(struct msm_gpu *gpu) hangcheck_timer_reset() argument
494 made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) made_progress() argument
511 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); hangcheck_handler() local
548 update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) update_hw_cntrs() argument
568 update_sw_cntrs(struct msm_gpu *gpu) update_sw_cntrs() argument
592 msm_gpu_perfcntr_start(struct msm_gpu *gpu) msm_gpu_perfcntr_start() argument
608 msm_gpu_perfcntr_stop(struct msm_gpu *gpu) msm_gpu_perfcntr_stop() argument
615 msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) msm_gpu_perfcntr_sample() argument
645 retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, struct msm_gem_submit *submit) retire_submit() argument
694 retire_submits(struct msm_gpu *gpu) retire_submits() argument
729 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); retire_worker() local
735 msm_gpu_retire(struct msm_gpu *gpu) msm_gpu_retire() argument
747 msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) msm_gpu_submit() argument
794 struct msm_gpu *gpu = data; irq_handler() local
798 get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) get_clocks() argument
820 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) msm_gpu_create_private_address_space() argument
842 msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config) msm_gpu_init() argument
997 msm_gpu_cleanup(struct msm_gpu *gpu) msm_gpu_cleanup() argument
[all...]
H A Dmsm_gpu_devfreq.c22 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_target() local
23 struct msm_gpu_devfreq *df = &gpu->devfreq; in msm_devfreq_target()
46 if (gpu->funcs->gpu_set_freq) { in msm_devfreq_target()
48 gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); in msm_devfreq_target()
59 static unsigned long get_freq(struct msm_gpu *gpu) in get_freq() argument
61 struct msm_gpu_devfreq *df = &gpu->devfreq; in get_freq()
71 if (gpu->funcs->gpu_get_freq) in get_freq()
72 return gpu->funcs->gpu_get_freq(gpu); in get_freq()
80 struct msm_gpu *gpu = dev_to_gpu(dev); msm_devfreq_get_dev_status() local
133 has_devfreq(struct msm_gpu *gpu) has_devfreq() argument
139 msm_devfreq_init(struct msm_gpu *gpu) msm_devfreq_init() argument
211 msm_devfreq_cleanup(struct msm_gpu *gpu) msm_devfreq_cleanup() argument
222 msm_devfreq_resume(struct msm_gpu *gpu) msm_devfreq_resume() argument
239 msm_devfreq_suspend(struct msm_gpu *gpu) msm_devfreq_suspend() argument
264 msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) msm_devfreq_boost() argument
288 msm_devfreq_active(struct msm_gpu *gpu) msm_devfreq_active() argument
339 struct msm_gpu *gpu = container_of(df, struct msm_gpu, devfreq); msm_devfreq_idle_work() local
360 msm_devfreq_idle(struct msm_gpu *gpu) msm_devfreq_idle() argument
[all...]
H A Dmsm_gpu.h47 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
49 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
51 int (*hw_init)(struct msm_gpu *gpu);
56 int (*ucode_load)(struct msm_gpu *gpu);
58 int (*pm_suspend)(struct msm_gpu *gpu);
59 int (*pm_resume)(struct msm_gpu *gpu);
60 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
61 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
63 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
64 void (*recover)(struct msm_gpu *gpu);
318 msm_gpu_active(struct msm_gpu *gpu) msm_gpu_active() argument
458 msm_gpu_convert_priority(struct msm_gpu *gpu, int prio, unsigned *ring_nr, enum drm_sched_priority *sched_prio) msm_gpu_convert_priority() argument
556 gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) gpu_write() argument
561 gpu_read(struct msm_gpu *gpu, u32 reg) gpu_read() argument
566 gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) gpu_rmw() argument
571 gpu_read64(struct msm_gpu *gpu, u32 reg) gpu_read64() argument
595 gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val) gpu_write64() argument
674 msm_gpu_crashstate_get(struct msm_gpu *gpu) msm_gpu_crashstate_get() argument
690 msm_gpu_crashstate_put(struct msm_gpu *gpu) msm_gpu_crashstate_put() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c31 { .name = "etnaviv-gpu,2d" },
39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
45 *value = gpu->identity.model; in etnaviv_gpu_get_param()
49 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
53 *value = gpu->identity.features; in etnaviv_gpu_get_param()
57 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
69 *value = gpu in etnaviv_gpu_get_param()
182 etnaviv_hw_specs(struct etnaviv_gpu *gpu) etnaviv_hw_specs() argument
332 etnaviv_hw_identify(struct etnaviv_gpu *gpu) etnaviv_hw_identify() argument
473 etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) etnaviv_gpu_load_clock() argument
480 etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) etnaviv_gpu_update_clock() argument
506 etnaviv_hw_reset(struct etnaviv_gpu *gpu) etnaviv_hw_reset() argument
596 etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) etnaviv_gpu_enable_mlcg() argument
650 etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) etnaviv_gpu_start_fe() argument
664 etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, struct etnaviv_iommu_context *context) etnaviv_gpu_start_fe_idleloop() argument
685 etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) etnaviv_gpu_setup_pulse_eater() argument
716 etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) etnaviv_gpu_hw_init() argument
771 etnaviv_gpu_init(struct etnaviv_gpu *gpu) etnaviv_gpu_init() argument
895 verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) verify_dma() argument
914 etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) etnaviv_gpu_debugfs() argument
1079 struct etnaviv_gpu *gpu; global() member
1121 etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) etnaviv_gpu_fence_alloc() argument
1153 event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, unsigned int *events) event_alloc() argument
1206 event_free(struct etnaviv_gpu *gpu, unsigned int event) event_free() argument
1222 etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, u32 id, struct drm_etnaviv_timespec *timeout) etnaviv_gpu_wait_fence_interruptible() argument
1269 etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, struct etnaviv_gem_object *etnaviv_obj, struct drm_etnaviv_timespec *timeout) etnaviv_gpu_wait_obj_inactive() argument
1292 sync_point_perfmon_sample(struct etnaviv_gpu *gpu, struct etnaviv_event *event, unsigned int flags) sync_point_perfmon_sample() argument
1306 sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, struct etnaviv_event *event) sync_point_perfmon_sample_pre() argument
1324 sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, struct etnaviv_event *event) sync_point_perfmon_sample_post() argument
1354 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_gpu_submit() local
1420 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, sync_point_worker() local
1435 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_gpu_recover_hang() local
1476 dump_mmu_fault(struct etnaviv_gpu *gpu) dump_mmu_fault() argument
1523 struct etnaviv_gpu *gpu = data; irq_handler() local
1589 etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) etnaviv_gpu_clk_enable() argument
1621 etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) etnaviv_gpu_clk_disable() argument
1631 etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) etnaviv_gpu_wait_idle() argument
1652 etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) etnaviv_gpu_hw_suspend() argument
1673 etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) etnaviv_gpu_hw_resume() argument
1702 struct etnaviv_gpu *gpu = cdev->devdata; etnaviv_gpu_cooling_get_cur_state() local
1713 struct etnaviv_gpu *gpu = cdev->devdata; etnaviv_gpu_cooling_set_cur_state() local
1735 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_bind() local
1789 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_unbind() local
1835 struct etnaviv_gpu *gpu; etnaviv_gpu_platform_probe() local
1916 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_rpm_suspend() local
1942 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_rpm_resume() local
[all...]
H A Detnaviv_sched.c28 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
37 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
42 drm_sched_stop(&gpu->sched, sched_job); in etnaviv_sched_timedout_job()
56 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
57 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
58 if (gpu->state == ETNA_GPU_STATE_RUNNING && in etnaviv_sched_timedout_job()
59 (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
61 gpu in etnaviv_sched_timedout_job()
101 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_sched_push_job() local
133 etnaviv_sched_init(struct etnaviv_gpu *gpu) etnaviv_sched_init() argument
147 etnaviv_sched_fini(struct etnaviv_gpu *gpu) etnaviv_sched_fini() argument
[all...]
H A Detnaviv_buffer.c90 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
95 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
103 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
105 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
116 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
122 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
124 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump()
152 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
159 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_reserve()
163 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument
180 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr) etnaviv_buffer_config_mmuv2() argument
215 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id) etnaviv_buffer_config_pta() argument
233 etnaviv_buffer_end(struct etnaviv_gpu *gpu) etnaviv_buffer_end() argument
301 etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) etnaviv_sync_point_queue() argument
340 etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, struct etnaviv_iommu_context *mmu_context, unsigned int event, struct etnaviv_cmdbuf *cmdbuf) etnaviv_buffer_queue() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c35 { .name = "etnaviv-gpu,2d" },
43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
49 *value = gpu->identity.model; in etnaviv_gpu_get_param()
53 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
57 *value = gpu->identity.features; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
73 *value = gpu in etnaviv_gpu_get_param()
174 etnaviv_hw_specs(struct etnaviv_gpu *gpu) etnaviv_hw_specs() argument
324 etnaviv_hw_identify(struct etnaviv_gpu *gpu) etnaviv_hw_identify() argument
465 etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) etnaviv_gpu_load_clock() argument
472 etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) etnaviv_gpu_update_clock() argument
490 etnaviv_hw_reset(struct etnaviv_gpu *gpu) etnaviv_hw_reset() argument
580 etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) etnaviv_gpu_enable_mlcg() argument
627 etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) etnaviv_gpu_start_fe() argument
643 etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, struct etnaviv_iommu_context *context) etnaviv_gpu_start_fe_idleloop() argument
660 etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) etnaviv_gpu_setup_pulse_eater() argument
691 etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) etnaviv_gpu_hw_init() argument
741 etnaviv_gpu_init(struct etnaviv_gpu *gpu) etnaviv_gpu_init() argument
857 verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) verify_dma() argument
876 etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) etnaviv_gpu_debugfs() argument
1037 etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) etnaviv_gpu_recover_hang() argument
1067 struct etnaviv_gpu *gpu; global() member
1109 etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) etnaviv_gpu_fence_alloc() argument
1141 event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, unsigned int *events) event_alloc() argument
1182 event_free(struct etnaviv_gpu *gpu, unsigned int event) event_free() argument
1196 etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, u32 id, struct drm_etnaviv_timespec *timeout) etnaviv_gpu_wait_fence_interruptible() argument
1243 etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, struct etnaviv_gem_object *etnaviv_obj, struct drm_etnaviv_timespec *timeout) etnaviv_gpu_wait_obj_inactive() argument
1266 sync_point_perfmon_sample(struct etnaviv_gpu *gpu, struct etnaviv_event *event, unsigned int flags) sync_point_perfmon_sample() argument
1280 sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, struct etnaviv_event *event) sync_point_perfmon_sample_pre() argument
1298 sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, struct etnaviv_event *event) sync_point_perfmon_sample_post() argument
1328 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_gpu_submit() local
1403 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, sync_point_worker() local
1416 dump_mmu_fault(struct etnaviv_gpu *gpu) dump_mmu_fault() argument
1447 struct etnaviv_gpu *gpu = data; irq_handler() local
1511 etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) etnaviv_gpu_clk_enable() argument
1543 etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) etnaviv_gpu_clk_disable() argument
1553 etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) etnaviv_gpu_wait_idle() argument
1574 etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) etnaviv_gpu_hw_suspend() argument
1598 etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) etnaviv_gpu_hw_resume() argument
1628 struct etnaviv_gpu *gpu = cdev->devdata; etnaviv_gpu_cooling_get_cur_state() local
1639 struct etnaviv_gpu *gpu = cdev->devdata; etnaviv_gpu_cooling_set_cur_state() local
1661 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_bind() local
1721 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_unbind() local
1770 struct etnaviv_gpu *gpu; etnaviv_gpu_platform_probe() local
1854 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_rpm_suspend() local
1876 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_rpm_resume() local
[all...]
H A Detnaviv_buffer.c89 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
94 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
102 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
104 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
115 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
121 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
123 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump()
151 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
158 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_reserve()
162 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument
179 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr) etnaviv_buffer_config_mmuv2() argument
214 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id) etnaviv_buffer_config_pta() argument
232 etnaviv_buffer_end(struct etnaviv_gpu *gpu) etnaviv_buffer_end() argument
300 etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) etnaviv_sync_point_queue() argument
339 etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, struct etnaviv_iommu_context *mmu_context, unsigned int event, struct etnaviv_cmdbuf *cmdbuf) etnaviv_buffer_queue() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
H A Dmsm_gpu.c27 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_target() local
37 if (gpu->funcs->gpu_set_freq) in msm_devfreq_target()
38 gpu->funcs->gpu_set_freq(gpu, opp); in msm_devfreq_target()
40 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
50 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_get_dev_status() local
53 if (gpu->funcs->gpu_get_freq) in msm_devfreq_get_dev_status()
54 status->current_frequency = gpu->funcs->gpu_get_freq(gpu); in msm_devfreq_get_dev_status()
56 status->current_frequency = clk_get_rate(gpu in msm_devfreq_get_dev_status()
69 struct msm_gpu *gpu = dev_to_gpu(dev); msm_devfreq_get_cur_freq() local
86 msm_devfreq_init(struct msm_gpu *gpu) msm_devfreq_init() argument
115 enable_pwrrail(struct msm_gpu *gpu) enable_pwrrail() argument
139 disable_pwrrail(struct msm_gpu *gpu) disable_pwrrail() argument
148 enable_clk(struct msm_gpu *gpu) enable_clk() argument
160 disable_clk(struct msm_gpu *gpu) disable_clk() argument
178 enable_axi(struct msm_gpu *gpu) enable_axi() argument
185 disable_axi(struct msm_gpu *gpu) disable_axi() argument
192 msm_gpu_resume_devfreq(struct msm_gpu *gpu) msm_gpu_resume_devfreq() argument
200 msm_gpu_pm_resume(struct msm_gpu *gpu) msm_gpu_pm_resume() argument
226 msm_gpu_pm_suspend(struct msm_gpu *gpu) msm_gpu_pm_suspend() argument
250 msm_gpu_hw_init(struct msm_gpu *gpu) msm_gpu_hw_init() argument
272 struct msm_gpu *gpu = data; msm_gpu_devcoredump_read() local
307 struct msm_gpu *gpu = data; msm_gpu_devcoredump_free() local
343 msm_gpu_crashstate_capture(struct msm_gpu *gpu, struct msm_gem_submit *submit, char *comm, char *cmd) msm_gpu_crashstate_capture() argument
404 msm_gpu_crashstate_capture(struct msm_gpu *gpu, struct msm_gem_submit *submit, char *comm, char *cmd) msm_gpu_crashstate_capture() argument
414 update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, uint32_t fence) update_fences() argument
446 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); recover_worker() local
536 hangcheck_timer_reset(struct msm_gpu *gpu) hangcheck_timer_reset() argument
545 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); hangcheck_handler() local
580 update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) update_hw_cntrs() argument
600 update_sw_cntrs(struct msm_gpu *gpu) update_sw_cntrs() argument
624 msm_gpu_perfcntr_start(struct msm_gpu *gpu) msm_gpu_perfcntr_start() argument
640 msm_gpu_perfcntr_stop(struct msm_gpu *gpu) msm_gpu_perfcntr_stop() argument
647 msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) msm_gpu_perfcntr_sample() argument
677 retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, struct msm_gem_submit *submit) retire_submit() argument
712 retire_submits(struct msm_gpu *gpu) retire_submits() argument
733 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); retire_worker() local
746 msm_gpu_retire(struct msm_gpu *gpu) msm_gpu_retire() argument
754 msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) msm_gpu_submit() argument
809 struct msm_gpu *gpu = data; irq_handler() local
813 get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) get_clocks() argument
835 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) msm_gpu_create_private_address_space() argument
857 msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config) msm_gpu_init() argument
989 msm_gpu_cleanup(struct msm_gpu *gpu) msm_gpu_cleanup() argument
[all...]
H A Dmsm_gpu.h45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
57 void (*show)(struct msm_gpu *gpu, struc
166 msm_gpu_active(struct msm_gpu *gpu) msm_gpu_active() argument
237 gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) gpu_write() argument
242 gpu_read(struct msm_gpu *gpu, u32 reg) gpu_read() argument
247 gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) gpu_rmw() argument
255 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) gpu_read64() argument
279 gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) gpu_write64() argument
319 msm_gpu_crashstate_get(struct msm_gpu *gpu) msm_gpu_crashstate_get() argument
335 msm_gpu_crashstate_put(struct msm_gpu *gpu) msm_gpu_crashstate_put() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
43 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a3xx_submit()
82 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
108 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
109 return a3xx_idle(gpu); in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
351 a3xx_recover(struct msm_gpu *gpu) a3xx_recover() argument
372 a3xx_destroy(struct msm_gpu *gpu) a3xx_destroy() argument
386 a3xx_idle(struct msm_gpu *gpu) a3xx_idle() argument
404 a3xx_irq(struct msm_gpu *gpu) a3xx_irq() argument
459 a3xx_dump(struct msm_gpu *gpu) a3xx_dump() argument
466 a3xx_gpu_state_get(struct msm_gpu *gpu) a3xx_gpu_state_get() argument
480 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) a3xx_gpu_busy() argument
490 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a3xx_get_rptr() argument
530 struct msm_gpu *gpu; a3xx_gpu_init() local
[all...]
H A Da5xx_power.c103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAG in a530_lm_setup()
175 a540_lm_setup(struct msm_gpu *gpu) a540_lm_setup() argument
211 a5xx_pc_init(struct msm_gpu *gpu) a5xx_pc_init() argument
220 a5xx_gpmu_init(struct msm_gpu *gpu) a5xx_gpmu_init() argument
278 a5xx_lm_enable(struct msm_gpu *gpu) a5xx_lm_enable() argument
295 a5xx_power_init(struct msm_gpu *gpu) a5xx_power_init() argument
324 a5xx_gpmu_ucode_init(struct msm_gpu *gpu) a5xx_gpmu_ucode_init() argument
[all...]
H A Dadreno_gpu.h69 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
144 * of gpu firmware to linux-firmware, the fw files were
202 static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) in adreno_patchid() argument
208 WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); in adreno_patchid()
209 return gpu->chip_id & 0xff; in adreno_patchid()
212 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) in adreno_is_revn() argument
214 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_revn()
216 return gpu->info->revn == revn; in adreno_is_revn()
219 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) in adreno_has_gmu_wrapper() argument
221 return gpu in adreno_has_gmu_wrapper()
224 adreno_is_a2xx(const struct adreno_gpu *gpu) adreno_is_a2xx() argument
231 adreno_is_a20x(const struct adreno_gpu *gpu) adreno_is_a20x() argument
238 adreno_is_a225(const struct adreno_gpu *gpu) adreno_is_a225() argument
243 adreno_is_a305(const struct adreno_gpu *gpu) adreno_is_a305() argument
248 adreno_is_a306(const struct adreno_gpu *gpu) adreno_is_a306() argument
254 adreno_is_a320(const struct adreno_gpu *gpu) adreno_is_a320() argument
259 adreno_is_a330(const struct adreno_gpu *gpu) adreno_is_a330() argument
264 adreno_is_a330v2(const struct adreno_gpu *gpu) adreno_is_a330v2() argument
269 adreno_is_a405(const struct adreno_gpu *gpu) adreno_is_a405() argument
274 adreno_is_a420(const struct adreno_gpu *gpu) adreno_is_a420() argument
279 adreno_is_a430(const struct adreno_gpu *gpu) adreno_is_a430() argument
284 adreno_is_a506(const struct adreno_gpu *gpu) adreno_is_a506() argument
289 adreno_is_a508(const struct adreno_gpu *gpu) adreno_is_a508() argument
294 adreno_is_a509(const struct adreno_gpu *gpu) adreno_is_a509() argument
299 adreno_is_a510(const struct adreno_gpu *gpu) adreno_is_a510() argument
304 adreno_is_a512(const struct adreno_gpu *gpu) adreno_is_a512() argument
309 adreno_is_a530(const struct adreno_gpu *gpu) adreno_is_a530() argument
314 adreno_is_a540(const struct adreno_gpu *gpu) adreno_is_a540() argument
319 adreno_is_a610(const struct adreno_gpu *gpu) adreno_is_a610() argument
324 adreno_is_a618(const struct adreno_gpu *gpu) adreno_is_a618() argument
329 adreno_is_a619(const struct adreno_gpu *gpu) adreno_is_a619() argument
334 adreno_is_a619_holi(const struct adreno_gpu *gpu) adreno_is_a619_holi() argument
339 adreno_is_a630(const struct adreno_gpu *gpu) adreno_is_a630() argument
344 adreno_is_a640(const struct adreno_gpu *gpu) adreno_is_a640() argument
349 adreno_is_a650(const struct adreno_gpu *gpu) adreno_is_a650() argument
354 adreno_is_7c3(const struct adreno_gpu *gpu) adreno_is_7c3() argument
359 adreno_is_a660(const struct adreno_gpu *gpu) adreno_is_a660() argument
364 adreno_is_a680(const struct adreno_gpu *gpu) adreno_is_a680() argument
369 adreno_is_a690(const struct adreno_gpu *gpu) adreno_is_a690() argument
375 adreno_is_a630_family(const struct adreno_gpu *gpu) adreno_is_a630_family() argument
382 adreno_is_a660_family(const struct adreno_gpu *gpu) adreno_is_a660_family() argument
390 adreno_is_a650_family(const struct adreno_gpu *gpu) adreno_is_a650_family() argument
397 adreno_is_a640_family(const struct adreno_gpu *gpu) adreno_is_a640_family() argument
[all...]
H A Da5xx_gpu.c17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
78 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a5xx_submit_in_rb()
112 a5xx_flush(gpu, rin in a5xx_submit_in_rb()
124 a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a5xx_submit() argument
436 a5xx_set_hwcg(struct msm_gpu *gpu, bool state) a5xx_set_hwcg() argument
466 a5xx_me_init(struct msm_gpu *gpu) a5xx_me_init() argument
507 a5xx_preempt_start(struct msm_gpu *gpu) a5xx_preempt_start() argument
570 a5xx_ucode_load(struct msm_gpu *gpu) a5xx_ucode_load() argument
632 a5xx_zap_shader_resume(struct msm_gpu *gpu) a5xx_zap_shader_resume() argument
652 a5xx_zap_shader_init(struct msm_gpu *gpu) a5xx_zap_shader_init() argument
683 a5xx_hw_init(struct msm_gpu *gpu) a5xx_hw_init() argument
1003 a5xx_recover(struct msm_gpu *gpu) a5xx_recover() argument
1023 a5xx_destroy(struct msm_gpu *gpu) a5xx_destroy() argument
1056 _a5xx_check_idle(struct msm_gpu *gpu) _a5xx_check_idle() argument
1069 a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a5xx_idle() argument
1098 struct msm_gpu *gpu = arg; a5xx_fault_handler() local
1114 a5xx_cp_err_irq(struct msm_gpu *gpu) a5xx_cp_err_irq() argument
1165 a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) a5xx_rbbm_err_irq() argument
1206 a5xx_uche_err_irq(struct msm_gpu *gpu) a5xx_uche_err_irq() argument
1216 a5xx_gpmu_err_irq(struct msm_gpu *gpu) a5xx_gpmu_err_irq() argument
1221 a5xx_fault_detect_irq(struct msm_gpu *gpu) a5xx_fault_detect_irq() argument
1259 a5xx_irq(struct msm_gpu *gpu) a5xx_irq() argument
1334 a5xx_dump(struct msm_gpu *gpu) a5xx_dump() argument
1341 a5xx_pm_resume(struct msm_gpu *gpu) a5xx_pm_resume() argument
1387 a5xx_pm_suspend(struct msm_gpu *gpu) a5xx_pm_suspend() argument
1426 a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a5xx_get_timestamp() argument
1444 a5xx_crashdumper_init(struct msm_gpu *gpu, struct a5xx_crashdumper *dumper) a5xx_crashdumper_init() argument
1457 a5xx_crashdumper_run(struct msm_gpu *gpu, struct a5xx_crashdumper *dumper) a5xx_crashdumper_run() argument
1500 a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, struct a5xx_gpu_state *a5xx_state) a5xx_gpu_state_get_hlsq_regs() argument
1559 a5xx_gpu_state_get(struct msm_gpu *gpu) a5xx_gpu_state_get() argument
1612 a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) a5xx_show() argument
1653 a5xx_active_ring(struct msm_gpu *gpu) a5xx_active_ring() argument
1661 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) a5xx_gpu_busy() argument
1671 a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a5xx_get_rptr() argument
1749 struct msm_gpu *gpu; a5xx_gpu_init() local
[all...]
H A Da4xx_gpu.c22 static void a4xx_dump(struct msm_gpu *gpu);
23 static bool a4xx_idle(struct msm_gpu *gpu);
25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit() argument
37 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a4xx_submit()
69 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit()
76 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
78 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_T in a4xx_enable_hwcg()
156 a4xx_me_init(struct msm_gpu *gpu) a4xx_me_init() argument
183 a4xx_hw_init(struct msm_gpu *gpu) a4xx_hw_init() argument
350 a4xx_recover(struct msm_gpu *gpu) a4xx_recover() argument
371 a4xx_destroy(struct msm_gpu *gpu) a4xx_destroy() argument
385 a4xx_idle(struct msm_gpu *gpu) a4xx_idle() argument
402 a4xx_irq(struct msm_gpu *gpu) a4xx_irq() argument
551 a4xx_gpu_state_get(struct msm_gpu *gpu) a4xx_gpu_state_get() argument
565 a4xx_dump(struct msm_gpu *gpu) a4xx_dump() argument
572 a4xx_pm_resume(struct msm_gpu *gpu) a4xx_pm_resume() argument
592 a4xx_pm_suspend(struct msm_gpu *gpu) a4xx_pm_suspend() argument
607 a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a4xx_get_timestamp() argument
614 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) a4xx_gpu_busy() argument
624 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a4xx_get_rptr() argument
658 struct msm_gpu *gpu; a4xx_gpu_init() local
[all...]
H A Da6xx_gpu.c18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
39 if (!adreno_idle(gpu, ring)) in a6xx_idle()
42 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
44 gpu->name, __builtin_return_address(0), in a6xx_idle()
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATU in a6xx_idle()
55 update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) update_shadow_rptr() argument
68 a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a6xx_flush() argument
172 a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_submit() argument
698 a6xx_set_hwcg(struct msm_gpu *gpu, bool state) a6xx_set_hwcg() argument
900 a6xx_set_cp_protect(struct msm_gpu *gpu) a6xx_set_cp_protect() argument
947 a6xx_set_ubwc_config(struct msm_gpu *gpu) a6xx_set_ubwc_config() argument
1023 a6xx_cp_init(struct msm_gpu *gpu) a6xx_cp_init() argument
1060 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_ucode_check_version() local
1119 a6xx_ucode_load(struct msm_gpu *gpu) a6xx_ucode_load() argument
1169 a6xx_zap_shader_init(struct msm_gpu *gpu) a6xx_zap_shader_init() argument
1195 hw_init(struct msm_gpu *gpu) hw_init() argument
1470 a6xx_hw_init(struct msm_gpu *gpu) a6xx_hw_init() argument
1483 a6xx_dump(struct msm_gpu *gpu) a6xx_dump() argument
1490 a6xx_recover(struct msm_gpu *gpu) a6xx_recover() argument
1566 a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) a6xx_uche_fault_block() argument
1594 a6xx_fault_block(struct msm_gpu *gpu, u32 id) a6xx_fault_block() argument
1608 struct msm_gpu *gpu = arg; a6xx_fault_handler() local
1625 a6xx_cp_hw_err_irq(struct msm_gpu *gpu) a6xx_cp_hw_err_irq() argument
1667 a6xx_fault_detect_irq(struct msm_gpu *gpu) a6xx_fault_detect_irq() argument
1706 a6xx_irq(struct msm_gpu *gpu) a6xx_irq() argument
1749 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_llc_activate() local
1854 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_bus_clear_pending_transactions() local
1889 a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) a6xx_gpu_sw_reset() argument
1905 a6xx_gmu_pm_resume(struct msm_gpu *gpu) a6xx_gmu_pm_resume() argument
1928 a6xx_pm_resume(struct msm_gpu *gpu) a6xx_pm_resume() argument
1979 a6xx_gmu_pm_suspend(struct msm_gpu *gpu) a6xx_gmu_pm_suspend() argument
2006 a6xx_pm_suspend(struct msm_gpu *gpu) a6xx_pm_suspend() argument
2042 a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a6xx_gmu_get_timestamp() argument
2061 a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a6xx_get_timestamp() argument
2067 a6xx_active_ring(struct msm_gpu *gpu) a6xx_active_ring() argument
2075 a6xx_destroy(struct msm_gpu *gpu) a6xx_destroy() argument
2099 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) a6xx_gpu_busy() argument
2115 a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended) a6xx_gpu_set_freq() argument
2127 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) a6xx_create_address_space() argument
2145 a6xx_create_private_address_space(struct msm_gpu *gpu) a6xx_create_private_address_space() argument
2159 a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a6xx_get_rptr() argument
2170 a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a6xx_progress() argument
2318 struct msm_gpu *gpu; a6xx_gpu_init() local
[all...]
H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
66 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
79 struct msm_gpu *gpu in a5xx_preempt_timer() local
90 a5xx_preempt_trigger(struct msm_gpu *gpu) a5xx_preempt_trigger() argument
157 a5xx_preempt_irq(struct msm_gpu *gpu) a5xx_preempt_irq() argument
193 a5xx_preempt_hw_init(struct msm_gpu *gpu) a5xx_preempt_hw_init() argument
224 struct msm_gpu *gpu = &adreno_gpu->base; preempt_init_ring() local
266 a5xx_preempt_fini(struct msm_gpu *gpu) a5xx_preempt_fini() argument
278 a5xx_preempt_init(struct msm_gpu *gpu) a5xx_preempt_init() argument
[all...]
H A Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
25 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a2xx_submit()
51 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
56 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a2xx_me_init()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
104 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
105 return a2xx_idle(gpu); in a2xx_me_init()
108 a2xx_hw_init(struct msm_gpu *gpu) a2xx_hw_init() argument
266 a2xx_recover(struct msm_gpu *gpu) a2xx_recover() argument
287 a2xx_destroy(struct msm_gpu *gpu) a2xx_destroy() argument
299 a2xx_idle(struct msm_gpu *gpu) a2xx_idle() argument
317 a2xx_irq(struct msm_gpu *gpu) a2xx_irq() argument
448 a2xx_dump(struct msm_gpu *gpu) a2xx_dump() argument
455 a2xx_gpu_state_get(struct msm_gpu *gpu) a2xx_gpu_state_get() argument
470 a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) a2xx_create_address_space() argument
484 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a2xx_get_rptr() argument
520 struct msm_gpu *gpu; a2xx_gpu_init() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
33 struct msm_drm_private *priv = gpu->dev->dev_private; in a3xx_submit()
83 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
86 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
88 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
109 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
110 return a3xx_idle(gpu); in a3xx_me_init()
113 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
352 a3xx_recover(struct msm_gpu *gpu) a3xx_recover() argument
373 a3xx_destroy(struct msm_gpu *gpu) a3xx_destroy() argument
387 a3xx_idle(struct msm_gpu *gpu) a3xx_idle() argument
405 a3xx_irq(struct msm_gpu *gpu) a3xx_irq() argument
460 a3xx_dump(struct msm_gpu *gpu) a3xx_dump() argument
467 a3xx_gpu_state_get(struct msm_gpu *gpu) a3xx_gpu_state_get() argument
481 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a3xx_get_rptr() argument
519 struct msm_gpu *gpu; a3xx_gpu_init() local
[all...]
H A Da5xx_power.c103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAG in a530_lm_setup()
175 a540_lm_setup(struct msm_gpu *gpu) a540_lm_setup() argument
211 a5xx_pc_init(struct msm_gpu *gpu) a5xx_pc_init() argument
220 a5xx_gpmu_init(struct msm_gpu *gpu) a5xx_gpmu_init() argument
278 a5xx_lm_enable(struct msm_gpu *gpu) a5xx_lm_enable() argument
295 a5xx_power_init(struct msm_gpu *gpu) a5xx_power_init() argument
324 a5xx_gpmu_ucode_init(struct msm_gpu *gpu) a5xx_gpmu_ucode_init() argument
[all...]
H A Da6xx_gpu.c15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
36 if (!adreno_idle(gpu, ring)) in a6xx_idle()
39 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
41 gpu->name, __builtin_return_address(0), in a6xx_idle()
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATU in a6xx_idle()
52 a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a6xx_flush() argument
138 a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_submit() argument
427 a6xx_set_hwcg(struct msm_gpu *gpu, bool state) a6xx_set_hwcg() argument
541 a6xx_set_cp_protect(struct msm_gpu *gpu) a6xx_set_cp_protect() argument
569 a6xx_set_ubwc_config(struct msm_gpu *gpu) a6xx_set_ubwc_config() argument
600 a6xx_cp_init(struct msm_gpu *gpu) a6xx_cp_init() argument
653 a6xx_ucode_init(struct msm_gpu *gpu) a6xx_ucode_init() argument
682 a6xx_zap_shader_init(struct msm_gpu *gpu) a6xx_zap_shader_init() argument
708 a6xx_hw_init(struct msm_gpu *gpu) a6xx_hw_init() argument
944 a6xx_dump(struct msm_gpu *gpu) a6xx_dump() argument
954 a6xx_recover(struct msm_gpu *gpu) a6xx_recover() argument
983 struct msm_gpu *gpu = arg; a6xx_fault_handler() local
995 a6xx_cp_hw_err_irq(struct msm_gpu *gpu) a6xx_cp_hw_err_irq() argument
1037 a6xx_fault_detect_irq(struct msm_gpu *gpu) a6xx_fault_detect_irq() argument
1068 a6xx_irq(struct msm_gpu *gpu) a6xx_irq() argument
1098 a6xx_pm_resume(struct msm_gpu *gpu) a6xx_pm_resume() argument
1117 a6xx_pm_suspend(struct msm_gpu *gpu) a6xx_pm_suspend() argument
1138 a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a6xx_get_timestamp() argument
1157 a6xx_active_ring(struct msm_gpu *gpu) a6xx_active_ring() argument
1165 a6xx_destroy(struct msm_gpu *gpu) a6xx_destroy() argument
1186 a6xx_gpu_busy(struct msm_gpu *gpu) a6xx_gpu_busy() argument
1215 a6xx_create_private_address_space(struct msm_gpu *gpu) a6xx_create_private_address_space() argument
1228 a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a6xx_get_rptr() argument
1276 struct msm_gpu *gpu; a6xx_gpu_init() local
[all...]
H A Da4xx_gpu.c22 static void a4xx_dump(struct msm_gpu *gpu);
23 static bool a4xx_idle(struct msm_gpu *gpu);
25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit() argument
27 struct msm_drm_private *priv = gpu->dev->dev_private; in a4xx_submit()
70 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit()
77 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
79 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
82 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
84 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
86 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_T in a4xx_enable_hwcg()
157 a4xx_me_init(struct msm_gpu *gpu) a4xx_me_init() argument
184 a4xx_hw_init(struct msm_gpu *gpu) a4xx_hw_init() argument
351 a4xx_recover(struct msm_gpu *gpu) a4xx_recover() argument
372 a4xx_destroy(struct msm_gpu *gpu) a4xx_destroy() argument
386 a4xx_idle(struct msm_gpu *gpu) a4xx_idle() argument
403 a4xx_irq(struct msm_gpu *gpu) a4xx_irq() argument
552 a4xx_gpu_state_get(struct msm_gpu *gpu) a4xx_gpu_state_get() argument
566 a4xx_dump(struct msm_gpu *gpu) a4xx_dump() argument
573 a4xx_pm_resume(struct msm_gpu *gpu) a4xx_pm_resume() argument
593 a4xx_pm_suspend(struct msm_gpu *gpu) a4xx_pm_suspend() argument
608 a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a4xx_get_timestamp() argument
616 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a4xx_get_rptr() argument
648 struct msm_gpu *gpu; a4xx_gpu_init() local
[all...]
H A Da5xx_gpu.c17 static void a5xx_dump(struct msm_gpu *gpu);
21 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
24 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
54 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
57 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
59 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb()
104 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
105 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb()
111 a5xx_idle(gpu, ring); in a5xx_submit_in_rb()
113 msm_gpu_retire(gpu); in a5xx_submit_in_rb()
116 a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a5xx_submit() argument
323 a5xx_set_hwcg(struct msm_gpu *gpu, bool state) a5xx_set_hwcg() argument
341 a5xx_me_init(struct msm_gpu *gpu) a5xx_me_init() argument
382 a5xx_preempt_start(struct msm_gpu *gpu) a5xx_preempt_start() argument
445 a5xx_ucode_init(struct msm_gpu *gpu) a5xx_ucode_init() argument
494 a5xx_zap_shader_resume(struct msm_gpu *gpu) a5xx_zap_shader_resume() argument
506 a5xx_zap_shader_init(struct msm_gpu *gpu) a5xx_zap_shader_init() argument
537 a5xx_hw_init(struct msm_gpu *gpu) a5xx_hw_init() argument
841 a5xx_recover(struct msm_gpu *gpu) a5xx_recover() argument
861 a5xx_destroy(struct msm_gpu *gpu) a5xx_destroy() argument
894 _a5xx_check_idle(struct msm_gpu *gpu) _a5xx_check_idle() argument
907 a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a5xx_idle() argument
936 struct msm_gpu *gpu = arg; a5xx_fault_handler() local
947 a5xx_cp_err_irq(struct msm_gpu *gpu) a5xx_cp_err_irq() argument
998 a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) a5xx_rbbm_err_irq() argument
1039 a5xx_uche_err_irq(struct msm_gpu *gpu) a5xx_uche_err_irq() argument
1049 a5xx_gpmu_err_irq(struct msm_gpu *gpu) a5xx_gpmu_err_irq() argument
1054 a5xx_fault_detect_irq(struct msm_gpu *gpu) a5xx_fault_detect_irq() argument
1084 a5xx_irq(struct msm_gpu *gpu) a5xx_irq() argument
1153 a5xx_dump(struct msm_gpu *gpu) a5xx_dump() argument
1160 a5xx_pm_resume(struct msm_gpu *gpu) a5xx_pm_resume() argument
1205 a5xx_pm_suspend(struct msm_gpu *gpu) a5xx_pm_suspend() argument
1241 a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) a5xx_get_timestamp() argument
1260 a5xx_crashdumper_init(struct msm_gpu *gpu, struct a5xx_crashdumper *dumper) a5xx_crashdumper_init() argument
1273 a5xx_crashdumper_run(struct msm_gpu *gpu, struct a5xx_crashdumper *dumper) a5xx_crashdumper_run() argument
1317 a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, struct a5xx_gpu_state *a5xx_state) a5xx_gpu_state_get_hlsq_regs() argument
1376 a5xx_gpu_state_get(struct msm_gpu *gpu) a5xx_gpu_state_get() argument
1423 a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) a5xx_show() argument
1464 a5xx_active_ring(struct msm_gpu *gpu) a5xx_active_ring() argument
1472 a5xx_gpu_busy(struct msm_gpu *gpu) a5xx_gpu_busy() argument
1496 a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) a5xx_get_rptr() argument
1571 struct msm_gpu *gpu; a5xx_gpu_init() local
[all...]
H A Dadreno_gpu.h47 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
85 * of gpu firmware to linux-firmware, the fw files were
141 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) in adreno_is_a2xx() argument
143 return (gpu->revn < 300); in adreno_is_a2xx()
146 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) in adreno_is_a20x() argument
148 return (gpu->revn < 210); in adreno_is_a20x()
151 static inline bool adreno_is_a225(struct adreno_gpu *gpu) in adreno_is_a225() argument
153 return gpu->revn == 225; in adreno_is_a225()
156 static inline bool adreno_is_a305(struct adreno_gpu *gpu) in adreno_is_a305() argument
158 return gpu in adreno_is_a305()
161 adreno_is_a306(struct adreno_gpu *gpu) adreno_is_a306() argument
167 adreno_is_a320(struct adreno_gpu *gpu) adreno_is_a320() argument
172 adreno_is_a330(struct adreno_gpu *gpu) adreno_is_a330() argument
177 adreno_is_a330v2(struct adreno_gpu *gpu) adreno_is_a330v2() argument
182 adreno_is_a405(struct adreno_gpu *gpu) adreno_is_a405() argument
187 adreno_is_a420(struct adreno_gpu *gpu) adreno_is_a420() argument
192 adreno_is_a430(struct adreno_gpu *gpu) adreno_is_a430() argument
197 adreno_is_a510(struct adreno_gpu *gpu) adreno_is_a510() argument
202 adreno_is_a530(struct adreno_gpu *gpu) adreno_is_a530() argument
207 adreno_is_a540(struct adreno_gpu *gpu) adreno_is_a540() argument
212 adreno_is_a618(struct adreno_gpu *gpu) adreno_is_a618() argument
217 adreno_is_a630(struct adreno_gpu *gpu) adreno_is_a630() argument
222 adreno_is_a640(struct adreno_gpu *gpu) adreno_is_a640() argument
227 adreno_is_a650(struct adreno_gpu *gpu) adreno_is_a650() argument
[all...]
H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
66 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
79 struct msm_gpu *gpu in a5xx_preempt_timer() local
91 a5xx_preempt_trigger(struct msm_gpu *gpu) a5xx_preempt_trigger() argument
159 a5xx_preempt_irq(struct msm_gpu *gpu) a5xx_preempt_irq() argument
196 a5xx_preempt_hw_init(struct msm_gpu *gpu) a5xx_preempt_hw_init() argument
228 struct msm_gpu *gpu = &adreno_gpu->base; preempt_init_ring() local
270 a5xx_preempt_fini(struct msm_gpu *gpu) a5xx_preempt_fini() argument
283 a5xx_preempt_init(struct msm_gpu *gpu) a5xx_preempt_init() argument
[all...]

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