Lines Matching refs:gpu
27 struct msm_gpu *gpu = dev_to_gpu(dev);
37 if (gpu->funcs->gpu_set_freq)
38 gpu->funcs->gpu_set_freq(gpu, opp);
40 clk_set_rate(gpu->core_clk, *freq);
50 struct msm_gpu *gpu = dev_to_gpu(dev);
53 if (gpu->funcs->gpu_get_freq)
54 status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
56 status->current_frequency = clk_get_rate(gpu->core_clk);
58 status->busy_time = gpu->funcs->gpu_busy(gpu);
61 status->total_time = ktime_us_delta(time, gpu->devfreq.time);
62 gpu->devfreq.time = time;
69 struct msm_gpu *gpu = dev_to_gpu(dev);
71 if (gpu->funcs->gpu_get_freq)
72 *freq = gpu->funcs->gpu_get_freq(gpu);
74 *freq = clk_get_rate(gpu->core_clk);
86 static void msm_devfreq_init(struct msm_gpu *gpu)
89 if (!gpu->funcs->gpu_busy)
92 msm_devfreq_profile.initial_freq = gpu->fast_rate;
103 gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
107 if (IS_ERR(gpu->devfreq.devfreq)) {
108 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
109 gpu->devfreq.devfreq = NULL;
112 devfreq_suspend_device(gpu->devfreq.devfreq);
115 static int enable_pwrrail(struct msm_gpu *gpu)
117 struct drm_device *dev = gpu->dev;
120 if (gpu->gpu_reg) {
121 ret = regulator_enable(gpu->gpu_reg);
128 if (gpu->gpu_cx) {
129 ret = regulator_enable(gpu->gpu_cx);
139 static int disable_pwrrail(struct msm_gpu *gpu)
141 if (gpu->gpu_cx)
142 regulator_disable(gpu->gpu_cx);
143 if (gpu->gpu_reg)
144 regulator_disable(gpu->gpu_reg);
148 static int enable_clk(struct msm_gpu *gpu)
150 if (gpu->core_clk && gpu->fast_rate)
151 clk_set_rate(gpu->core_clk, gpu->fast_rate);
154 if (gpu->rbbmtimer_clk)
155 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
157 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
160 static int disable_clk(struct msm_gpu *gpu)
162 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
169 if (gpu->core_clk)
170 clk_set_rate(gpu->core_clk, 27000000);
172 if (gpu->rbbmtimer_clk)
173 clk_set_rate(gpu->rbbmtimer_clk, 0);
178 static int enable_axi(struct msm_gpu *gpu)
180 if (gpu->ebi1_clk)
181 clk_prepare_enable(gpu->ebi1_clk);
185 static int disable_axi(struct msm_gpu *gpu)
187 if (gpu->ebi1_clk)
188 clk_disable_unprepare(gpu->ebi1_clk);
192 void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
194 gpu->devfreq.busy_cycles = 0;
195 gpu->devfreq.time = ktime_get();
197 devfreq_resume_device(gpu->devfreq.devfreq);
200 int msm_gpu_pm_resume(struct msm_gpu *gpu)
204 DBG("%s", gpu->name);
207 ret = enable_pwrrail(gpu);
211 ret = enable_clk(gpu);
215 ret = enable_axi(gpu);
219 msm_gpu_resume_devfreq(gpu);
221 gpu->needs_hw_init = true;
226 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
230 DBG("%s", gpu->name);
233 devfreq_suspend_device(gpu->devfreq.devfreq);
235 ret = disable_axi(gpu);
239 ret = disable_clk(gpu);
243 ret = disable_pwrrail(gpu);
250 int msm_gpu_hw_init(struct msm_gpu *gpu)
254 WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
256 if (!gpu->needs_hw_init)
259 disable_irq(gpu->irq);
260 ret = gpu->funcs->hw_init(gpu);
262 gpu->needs_hw_init = false;
263 enable_irq(gpu->irq);
272 struct msm_gpu *gpu = data;
277 state = msm_gpu_crashstate_get(gpu);
298 gpu->funcs->show(gpu, state, &p);
300 msm_gpu_crashstate_put(gpu);
307 struct msm_gpu *gpu = data;
309 msm_gpu_crashstate_put(gpu);
343 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
349 if (!gpu->funcs->gpu_state_get)
353 if (gpu->crashstate)
356 state = gpu->funcs->gpu_state_get(gpu);
397 gpu->crashstate = state;
400 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
404 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
411 * Hangcheck detection for locked gpu:
414 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
433 WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
442 static void retire_submits(struct msm_gpu *gpu);
446 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
447 struct drm_device *dev = gpu->dev;
450 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
456 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
463 gpu->global_faults++;
475 gpu->name, comm, cmd);
484 pm_runtime_get_sync(&gpu->pdev->dev);
485 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
486 pm_runtime_put_sync(&gpu->pdev->dev);
496 for (i = 0; i < gpu->nr_rings; i++) {
497 struct msm_ringbuffer *ring = gpu->rb[i];
508 update_fences(gpu, ring, fence);
511 if (msm_gpu_active(gpu)) {
513 retire_submits(gpu);
515 pm_runtime_get_sync(&gpu->pdev->dev);
516 gpu->funcs->recover(gpu);
517 pm_runtime_put_sync(&gpu->pdev->dev);
523 for (i = 0; i < gpu->nr_rings; i++) {
524 struct msm_ringbuffer *ring = gpu->rb[i];
527 gpu->funcs->submit(gpu, submit);
533 msm_gpu_retire(gpu);
536 static void hangcheck_timer_reset(struct msm_gpu *gpu)
538 DBG("%s", gpu->name);
539 mod_timer(&gpu->hangcheck_timer,
545 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
546 struct drm_device *dev = gpu->dev;
548 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
557 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
558 gpu->name, ring->id);
560 gpu->name, fence);
562 gpu->name, ring->seqno);
564 queue_work(priv->wq, &gpu->recover_work);
569 hangcheck_timer_reset(gpu);
572 queue_work(priv->wq, &gpu->retire_work);
580 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
582 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
583 int i, n = min(ncntrs, gpu->num_perfcntrs);
586 for (i = 0; i < gpu->num_perfcntrs; i++)
587 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
591 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
594 for (i = 0; i < gpu->num_perfcntrs; i++)
595 gpu->last_cntrs[i] = current_cntrs[i];
600 static void update_sw_cntrs(struct msm_gpu *gpu)
606 spin_lock_irqsave(&gpu->perf_lock, flags);
607 if (!gpu->perfcntr_active)
611 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
613 gpu->totaltime += elapsed;
614 if (gpu->last_sample.active)
615 gpu->activetime += elapsed;
617 gpu->last_sample.active = msm_gpu_active(gpu);
618 gpu->last_sample.time = time;
621 spin_unlock_irqrestore(&gpu->perf_lock, flags);
624 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
628 pm_runtime_get_sync(&gpu->pdev->dev);
630 spin_lock_irqsave(&gpu->perf_lock, flags);
632 gpu->last_sample.active = msm_gpu_active(gpu);
633 gpu->last_sample.time = ktime_get();
634 gpu->activetime = gpu->totaltime = 0;
635 gpu->perfcntr_active = true;
636 update_hw_cntrs(gpu, 0, NULL);
637 spin_unlock_irqrestore(&gpu->perf_lock, flags);
640 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
642 gpu->perfcntr_active = false;
643 pm_runtime_put_sync(&gpu->pdev->dev);
647 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
653 spin_lock_irqsave(&gpu->perf_lock, flags);
655 if (!gpu->perfcntr_active) {
660 *activetime = gpu->activetime;
661 *totaltime = gpu->totaltime;
663 gpu->activetime = gpu->totaltime = 0;
665 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
668 spin_unlock_irqrestore(&gpu->perf_lock, flags);
677 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
707 pm_runtime_mark_last_busy(&gpu->pdev->dev);
708 pm_runtime_put_autosuspend(&gpu->pdev->dev);
712 static void retire_submits(struct msm_gpu *gpu)
714 struct drm_device *dev = gpu->dev;
721 for (i = 0; i < gpu->nr_rings; i++) {
722 struct msm_ringbuffer *ring = gpu->rb[i];
726 retire_submit(gpu, ring, submit);
733 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
734 struct drm_device *dev = gpu->dev;
737 for (i = 0; i < gpu->nr_rings; i++)
738 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
741 retire_submits(gpu);
746 void msm_gpu_retire(struct msm_gpu *gpu)
748 struct msm_drm_private *priv = gpu->dev->dev_private;
749 queue_work(priv->wq, &gpu->retire_work);
750 update_sw_cntrs(gpu);
753 /* add bo's to gpu's ring, and kick gpu: */
754 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
756 struct drm_device *dev = gpu->dev;
763 pm_runtime_get_sync(&gpu->pdev->dev);
765 msm_gpu_hw_init(gpu);
773 update_sw_cntrs(gpu);
783 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
794 msm_gem_active_get(drm_obj, gpu);
797 gpu->funcs->submit(gpu, submit);
800 hangcheck_timer_reset(gpu);
809 struct msm_gpu *gpu = data;
810 return gpu->funcs->irq(gpu);
813 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
815 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
818 gpu->nr_clocks = 0;
822 gpu->nr_clocks = ret;
824 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
825 gpu->nr_clocks, "core");
827 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
828 gpu->nr_clocks, "rbbmtimer");
835 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
838 if (!gpu)
845 if (gpu->funcs->create_private_address_space) {
846 aspace = gpu->funcs->create_private_address_space(gpu);
852 aspace = msm_gem_address_space_get(gpu->aspace);
858 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
865 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
866 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
868 gpu->dev = drm;
869 gpu->funcs = funcs;
870 gpu->name = name;
872 INIT_LIST_HEAD(&gpu->active_list);
873 INIT_WORK(&gpu->retire_work, retire_worker);
874 INIT_WORK(&gpu->recover_work, recover_worker);
877 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
879 spin_lock_init(&gpu->perf_lock);
883 gpu->mmio = msm_ioremap(pdev, config->ioname, name);
884 if (IS_ERR(gpu->mmio)) {
885 ret = PTR_ERR(gpu->mmio);
890 gpu->irq = platform_get_irq(pdev, 0);
891 if (gpu->irq < 0) {
892 ret = gpu->irq;
897 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
898 IRQF_TRIGGER_HIGH, gpu->name, gpu);
900 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
904 ret = get_clocks(pdev, gpu);
908 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
909 DBG("ebi1_clk: %p", gpu->ebi1_clk);
910 if (IS_ERR(gpu->ebi1_clk))
911 gpu->ebi1_clk = NULL;
914 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
915 DBG("gpu_reg: %p", gpu->gpu_reg);
916 if (IS_ERR(gpu->gpu_reg))
917 gpu->gpu_reg = NULL;
919 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
920 DBG("gpu_cx: %p", gpu->gpu_cx);
921 if (IS_ERR(gpu->gpu_cx))
922 gpu->gpu_cx = NULL;
924 gpu->pdev = pdev;
925 platform_set_drvdata(pdev, &gpu->adreno_smmu);
927 msm_devfreq_init(gpu);
930 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
932 if (gpu->aspace == NULL)
934 else if (IS_ERR(gpu->aspace)) {
935 ret = PTR_ERR(gpu->aspace);
941 check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
950 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
952 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
954 ARRAY_SIZE(gpu->rb));
955 nr_rings = ARRAY_SIZE(gpu->rb);
960 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
962 if (IS_ERR(gpu->rb[i])) {
963 ret = PTR_ERR(gpu->rb[i]);
973 gpu->nr_rings = nr_rings;
978 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
979 msm_ringbuffer_destroy(gpu->rb[i]);
980 gpu->rb[i] = NULL;
983 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
989 void msm_gpu_cleanup(struct msm_gpu *gpu)
993 DBG("%s", gpu->name);
995 WARN_ON(!list_empty(&gpu->active_list));
997 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
998 msm_ringbuffer_destroy(gpu->rb[i]);
999 gpu->rb[i] = NULL;
1002 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
1004 if (!IS_ERR_OR_NULL(gpu->aspace)) {
1005 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
1006 msm_gem_address_space_put(gpu->aspace);