Lines Matching refs:gpu
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
57 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
60 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
62 unsigned long (*gpu_busy)(struct msm_gpu *gpu);
63 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
65 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
66 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
68 (struct msm_gpu *gpu, struct platform_device *pdev);
70 (struct msm_gpu *gpu);
71 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
100 /* does gpu need hw_init? */
166 static inline bool msm_gpu_active(struct msm_gpu *gpu)
170 for (i = 0; i < gpu->nr_rings; i++) {
171 struct msm_ringbuffer *ring = gpu->rb[i];
237 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
239 msm_writel(data, gpu->mmio + (reg << 2));
242 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
244 return msm_readl(gpu->mmio + (reg << 2));
247 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
249 uint32_t val = gpu_read(gpu, reg);
252 gpu_write(gpu, reg, val | or);
255 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
273 val = (u64) msm_readl(gpu->mmio + (lo << 2));
274 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
279 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
282 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
283 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
286 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
287 int msm_gpu_pm_resume(struct msm_gpu *gpu);
288 void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
290 int msm_gpu_hw_init(struct msm_gpu *gpu);
292 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
293 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
294 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
297 void msm_gpu_retire(struct msm_gpu *gpu);
298 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
301 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
305 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
307 void msm_gpu_cleanup(struct msm_gpu *gpu);
319 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
323 mutex_lock(&gpu->dev->struct_mutex);
325 if (gpu->crashstate) {
326 kref_get(&gpu->crashstate->ref);
327 state = gpu->crashstate;
330 mutex_unlock(&gpu->dev->struct_mutex);
335 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
337 mutex_lock(&gpu->dev->struct_mutex);
339 if (gpu->crashstate) {
340 if (gpu->funcs->gpu_state_put(gpu->crashstate))
341 gpu->crashstate = NULL;
344 mutex_unlock(&gpu->dev->struct_mutex);
351 #define check_apriv(gpu, flags) \
352 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))