Lines Matching refs:gpu
25 static int enable_pwrrail(struct msm_gpu *gpu)
27 struct drm_device *dev = gpu->dev;
30 if (gpu->gpu_reg) {
31 ret = regulator_enable(gpu->gpu_reg);
38 if (gpu->gpu_cx) {
39 ret = regulator_enable(gpu->gpu_cx);
49 static int disable_pwrrail(struct msm_gpu *gpu)
51 if (gpu->gpu_cx)
52 regulator_disable(gpu->gpu_cx);
53 if (gpu->gpu_reg)
54 regulator_disable(gpu->gpu_reg);
58 static int enable_clk(struct msm_gpu *gpu)
60 if (gpu->core_clk && gpu->fast_rate)
61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate);
64 if (gpu->rbbmtimer_clk)
65 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
70 static int disable_clk(struct msm_gpu *gpu)
72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
79 if (gpu->core_clk)
80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000);
82 if (gpu->rbbmtimer_clk)
83 clk_set_rate(gpu->rbbmtimer_clk, 0);
88 static int enable_axi(struct msm_gpu *gpu)
90 return clk_prepare_enable(gpu->ebi1_clk);
93 static int disable_axi(struct msm_gpu *gpu)
95 clk_disable_unprepare(gpu->ebi1_clk);
99 int msm_gpu_pm_resume(struct msm_gpu *gpu)
103 DBG("%s", gpu->name);
106 ret = enable_pwrrail(gpu);
110 ret = enable_clk(gpu);
114 ret = enable_axi(gpu);
118 msm_devfreq_resume(gpu);
120 gpu->needs_hw_init = true;
125 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
129 DBG("%s", gpu->name);
132 msm_devfreq_suspend(gpu);
134 ret = disable_axi(gpu);
138 ret = disable_clk(gpu);
142 ret = disable_pwrrail(gpu);
146 gpu->suspend_count++;
151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
154 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
155 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
156 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
159 int msm_gpu_hw_init(struct msm_gpu *gpu)
163 WARN_ON(!mutex_is_locked(&gpu->lock));
165 if (!gpu->needs_hw_init)
168 disable_irq(gpu->irq);
169 ret = gpu->funcs->hw_init(gpu);
171 gpu->needs_hw_init = false;
172 enable_irq(gpu->irq);
181 struct msm_gpu *gpu = data;
186 state = msm_gpu_crashstate_get(gpu);
207 gpu->funcs->show(gpu, state, &p);
209 msm_gpu_crashstate_put(gpu);
216 struct msm_gpu *gpu = data;
218 msm_gpu_crashstate_put(gpu);
257 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
263 if (!gpu->funcs->gpu_state_get)
267 if (gpu->crashstate)
270 state = gpu->funcs->gpu_state_get(gpu);
277 state->fault_info = gpu->fault_info;
293 gpu->crashstate = state;
296 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
300 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
307 * Hangcheck detection for locked gpu:
328 static void retire_submits(struct msm_gpu *gpu);
335 WARN_ON(!mutex_is_locked(&submit->gpu->lock));
356 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
357 struct drm_device *dev = gpu->dev;
360 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
364 mutex_lock(&gpu->lock);
366 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
379 gpu->name, comm, cmd);
391 gpu->global_faults++;
395 pm_runtime_get_sync(&gpu->pdev->dev);
396 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
406 for (i = 0; i < gpu->nr_rings; i++) {
407 struct msm_ringbuffer *ring = gpu->rb[i];
421 if (msm_gpu_active(gpu)) {
423 retire_submits(gpu);
425 gpu->funcs->recover(gpu);
431 for (i = 0; i < gpu->nr_rings; i++) {
432 struct msm_ringbuffer *ring = gpu->rb[i];
437 gpu->funcs->submit(gpu, submit);
442 pm_runtime_put(&gpu->pdev->dev);
444 mutex_unlock(&gpu->lock);
446 msm_gpu_retire(gpu);
451 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
453 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
456 mutex_lock(&gpu->lock);
473 pm_runtime_get_sync(&gpu->pdev->dev);
474 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
475 pm_runtime_put_sync(&gpu->pdev->dev);
481 memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
482 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
484 mutex_unlock(&gpu->lock);
487 static void hangcheck_timer_reset(struct msm_gpu *gpu)
489 struct msm_drm_private *priv = gpu->dev->dev_private;
490 mod_timer(&gpu->hangcheck_timer,
494 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
499 if (!gpu->funcs->progress)
502 if (!gpu->funcs->progress(gpu, ring))
511 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
512 struct drm_device *dev = gpu->dev;
513 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
521 !made_progress(gpu, ring)) {
525 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
526 gpu->name, ring->id);
528 gpu->name, fence);
530 gpu->name, ring->fctx->last_fence);
532 kthread_queue_work(gpu->worker, &gpu->recover_work);
537 hangcheck_timer_reset(gpu);
540 msm_gpu_retire(gpu);
548 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
550 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
551 int i, n = min(ncntrs, gpu->num_perfcntrs);
554 for (i = 0; i < gpu->num_perfcntrs; i++)
555 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
559 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
562 for (i = 0; i < gpu->num_perfcntrs; i++)
563 gpu->last_cntrs[i] = current_cntrs[i];
568 static void update_sw_cntrs(struct msm_gpu *gpu)
574 spin_lock_irqsave(&gpu->perf_lock, flags);
575 if (!gpu->perfcntr_active)
579 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
581 gpu->totaltime += elapsed;
582 if (gpu->last_sample.active)
583 gpu->activetime += elapsed;
585 gpu->last_sample.active = msm_gpu_active(gpu);
586 gpu->last_sample.time = time;
589 spin_unlock_irqrestore(&gpu->perf_lock, flags);
592 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
596 pm_runtime_get_sync(&gpu->pdev->dev);
598 spin_lock_irqsave(&gpu->perf_lock, flags);
600 gpu->last_sample.active = msm_gpu_active(gpu);
601 gpu->last_sample.time = ktime_get();
602 gpu->activetime = gpu->totaltime = 0;
603 gpu->perfcntr_active = true;
604 update_hw_cntrs(gpu, 0, NULL);
605 spin_unlock_irqrestore(&gpu->perf_lock, flags);
608 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
610 gpu->perfcntr_active = false;
611 pm_runtime_put_sync(&gpu->pdev->dev);
615 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
621 spin_lock_irqsave(&gpu->perf_lock, flags);
623 if (!gpu->perfcntr_active) {
628 *activetime = gpu->activetime;
629 *totaltime = gpu->totaltime;
631 gpu->activetime = gpu->totaltime = 0;
633 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
636 spin_unlock_irqrestore(&gpu->perf_lock, flags);
645 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
674 pm_runtime_mark_last_busy(&gpu->pdev->dev);
681 mutex_lock(&gpu->active_lock);
682 gpu->active_submits--;
683 WARN_ON(gpu->active_submits < 0);
684 if (!gpu->active_submits) {
685 msm_devfreq_idle(gpu);
686 pm_runtime_put_autosuspend(&gpu->pdev->dev);
689 mutex_unlock(&gpu->active_lock);
694 static void retire_submits(struct msm_gpu *gpu)
699 for (i = 0; i < gpu->nr_rings; i++) {
700 struct msm_ringbuffer *ring = gpu->rb[i];
717 retire_submit(gpu, ring, submit);
724 wake_up_all(&gpu->retire_event);
729 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
731 retire_submits(gpu);
735 void msm_gpu_retire(struct msm_gpu *gpu)
739 for (i = 0; i < gpu->nr_rings; i++)
740 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
742 kthread_queue_work(gpu->worker, &gpu->retire_work);
743 update_sw_cntrs(gpu);
746 /* add bo's to gpu's ring, and kick gpu: */
747 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
752 WARN_ON(!mutex_is_locked(&gpu->lock));
754 pm_runtime_get_sync(&gpu->pdev->dev);
756 msm_gpu_hw_init(gpu);
760 update_sw_cntrs(gpu);
773 mutex_lock(&gpu->active_lock);
774 if (!gpu->active_submits) {
775 pm_runtime_get(&gpu->pdev->dev);
776 msm_devfreq_active(gpu);
778 gpu->active_submits++;
779 mutex_unlock(&gpu->active_lock);
781 gpu->funcs->submit(gpu, submit);
782 gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
784 pm_runtime_put(&gpu->pdev->dev);
785 hangcheck_timer_reset(gpu);
794 struct msm_gpu *gpu = data;
795 return gpu->funcs->irq(gpu);
798 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
800 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
803 gpu->nr_clocks = 0;
807 gpu->nr_clocks = ret;
809 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
810 gpu->nr_clocks, "core");
812 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
813 gpu->nr_clocks, "rbbmtimer");
820 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
823 if (!gpu)
830 if (gpu->funcs->create_private_address_space) {
831 aspace = gpu->funcs->create_private_address_space(gpu);
837 aspace = msm_gem_address_space_get(gpu->aspace);
843 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
851 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
852 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
854 gpu->dev = drm;
855 gpu->funcs = funcs;
856 gpu->name = name;
858 gpu->worker = kthread_create_worker(0, "gpu-worker");
859 if (IS_ERR(gpu->worker)) {
860 ret = PTR_ERR(gpu->worker);
861 gpu->worker = NULL;
865 sched_set_fifo_low(gpu->worker->task);
867 mutex_init(&gpu->active_lock);
868 mutex_init(&gpu->lock);
869 init_waitqueue_head(&gpu->retire_event);
870 kthread_init_work(&gpu->retire_work, retire_worker);
871 kthread_init_work(&gpu->recover_work, recover_worker);
872 kthread_init_work(&gpu->fault_work, fault_worker);
884 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
886 spin_lock_init(&gpu->perf_lock);
890 gpu->mmio = msm_ioremap(pdev, config->ioname);
891 if (IS_ERR(gpu->mmio)) {
892 ret = PTR_ERR(gpu->mmio);
897 gpu->irq = platform_get_irq(pdev, 0);
898 if (gpu->irq < 0) {
899 ret = gpu->irq;
903 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
904 IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
906 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
910 ret = get_clocks(pdev, gpu);
914 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
915 DBG("ebi1_clk: %p", gpu->ebi1_clk);
916 if (IS_ERR(gpu->ebi1_clk))
917 gpu->ebi1_clk = NULL;
920 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
921 DBG("gpu_reg: %p", gpu->gpu_reg);
922 if (IS_ERR(gpu->gpu_reg))
923 gpu->gpu_reg = NULL;
925 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
926 DBG("gpu_cx: %p", gpu->gpu_cx);
927 if (IS_ERR(gpu->gpu_cx))
928 gpu->gpu_cx = NULL;
930 gpu->pdev = pdev;
931 platform_set_drvdata(pdev, &gpu->adreno_smmu);
933 msm_devfreq_init(gpu);
936 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
938 if (gpu->aspace == NULL)
940 else if (IS_ERR(gpu->aspace)) {
941 ret = PTR_ERR(gpu->aspace);
947 check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
956 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
958 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
960 ARRAY_SIZE(gpu->rb));
961 nr_rings = ARRAY_SIZE(gpu->rb);
966 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
968 if (IS_ERR(gpu->rb[i])) {
969 ret = PTR_ERR(gpu->rb[i]);
979 gpu->nr_rings = nr_rings;
981 refcount_set(&gpu->sysprof_active, 1);
986 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
987 msm_ringbuffer_destroy(gpu->rb[i]);
988 gpu->rb[i] = NULL;
991 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
997 void msm_gpu_cleanup(struct msm_gpu *gpu)
1001 DBG("%s", gpu->name);
1003 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1004 msm_ringbuffer_destroy(gpu->rb[i]);
1005 gpu->rb[i] = NULL;
1008 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
1010 if (!IS_ERR_OR_NULL(gpu->aspace)) {
1011 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
1012 msm_gem_address_space_put(gpu->aspace);
1015 if (gpu->worker) {
1016 kthread_destroy_worker(gpu->worker);
1019 msm_devfreq_cleanup(gpu);
1021 platform_set_drvdata(gpu->pdev, NULL);