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Searched refs:dpll (Results 1 - 25 of 96) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
325 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
327 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
342 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
354 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
373 const struct dpll *clock) in intel_pll_is_valid()
444 const struct dpll *match_cloc in i9xx_find_best_dpll()
776 i9xx_dpll_compute_fp(const struct dpll *dpll) i9xx_dpll_compute_fp() argument
781 pnv_dpll_compute_fp(const struct dpll *dpll) pnv_dpll_compute_fp() argument
812 u32 dpll; i9xx_compute_dpll() local
891 u32 dpll; i8xx_compute_dpll() local
1025 ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) ilk_needs_fb_cb_tune() argument
1069 u32 dpll; ilk_compute_dpll() local
1585 u32 dpll = crtc_state->dpll_hw_state.dpll; i9xx_enable_pll() local
1970 vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, const struct dpll *dpll) vlv_force_pll_on() argument
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H A Dintel_dpll.h11 struct dpll;
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
31 const struct dpll *dpll);
41 struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_cloc
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H A Dintel_dpll_mgr.c120 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
121 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
122 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
157 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
232 mutex_lock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
258 mutex_unlock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
281 mutex_lock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
304 mutex_unlock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
323 pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_find_shared_dpll()
451 * This is the dpll versio
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/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c105 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
154 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
155 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= in psb_intel_crtc_mode_set()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
173 dpll | in psb_intel_crtc_mode_set()
304 u32 dpll; psb_intel_crtc_clock_get() local
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H A Doaktrail_crtc.c242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
318 REG_READ_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
370 u32 dpll = 0, fp = 0, dspcntr, pipeconf; oaktrail_crtc_mode_set() local
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H A Dmdfld_intel_display.c243 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
249 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
250 REG_READ(map->dpll); in mdfld_disable_crtc()
257 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
299 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
306 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
311 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
312 REG_READ(map->dpll); in mdfld_crtc_dpms()
316 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
317 REG_READ(map->dpll); in mdfld_crtc_dpms()
649 u32 dpll = 0, fp = 0; mdfld_crtc_mode_set() local
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H A Dmdfld_device.c188 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
242 u32 dpll; in mdfld_restore_display_registers() local
249 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
274 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
275 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
280 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
282 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
286 if (dpll in mdfld_restore_display_registers()
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H A Dcdv_intel_display.c583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
662 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
665 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ in cdv_intel_crtc_mode_set()
666 dpll |= 3; in cdv_intel_crtc_mode_set()
668 /* dpll |= PLL_REF_INPUT_DREFCLK; */ in cdv_intel_crtc_mode_set()
679 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
681 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
683 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
684 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
725 REG_WRITE(map->dpll, dpl in cdv_intel_crtc_mode_set()
845 u32 dpll; cdv_intel_crtc_clock_get() local
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H A Dgma_display.c215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
303 temp = REG_READ(map->dpll); in gma_crtc_dpms()
305 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
306 REG_READ(map->dpll); in gma_crtc_dpms()
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H A Doaktrail_hdmi.c282 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
291 /* Disable dpll if necessary */ in oaktrail_crtc_hdmi_mode_set()
292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
293 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
303 /* program and enable dpll */ in oaktrail_crtc_hdmi_mode_set()
308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
310 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_CTRL, (dpll | (cloc in oaktrail_crtc_hdmi_mode_set()
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/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
163 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
167 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
179 dpll | in psb_intel_crtc_mode_set()
310 u32 dpll; psb_intel_crtc_clock_get() local
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H A Doaktrail_crtc.c245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
321 REG_READ_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
373 u32 dpll = 0, fp = 0, dspcntr, pipeconf; oaktrail_crtc_mode_set() local
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H A Dcdv_intel_display.c584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
678 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
680 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
681 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll | in cdv_intel_crtc_mode_set()
842 u32 dpll; cdv_intel_crtc_clock_get() local
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H A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
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H A Doaktrail_hdmi.c285 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
294 /* Disable dpll if necessary */ in oaktrail_crtc_hdmi_mode_set()
295 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
296 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
297 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
306 /* program and enable dpll */ in oaktrail_crtc_hdmi_mode_set()
311 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
312 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_CTRL, (dpll | (cloc in oaktrail_crtc_hdmi_mode_set()
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/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c70 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
107 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
122 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
126 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
163 * intel_prepare_shared_dpll - call a dpll's prepare hook
164 * @crtc_state: CRTC, and its state, which has a shared dpll
178 mutex_lock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
187 mutex_unlock(&dev_priv->dpll in intel_prepare_shared_dpll()
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H A Dintel_display.c578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
619 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
638 const struct dpll *clock) in intel_pll_is_valid()
711 int target, int refclk, struct dpll *match_cloc in i9xx_find_best_dpll()
1516 u32 dpll = crtc_state->dpll_hw_state.dpll; i9xx_enable_pll() local
8232 pnv_dpll_compute_fp(struct dpll *dpll) pnv_dpll_compute_fp() argument
8237 i9xx_dpll_compute_fp(struct dpll *dpll) i9xx_dpll_compute_fp() argument
8640 vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, const struct dpll *dpll) vlv_force_pll_on() argument
8690 u32 dpll; i9xx_compute_dpll() local
8764 u32 dpll; i8xx_compute_dpll() local
10247 ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) ilk_needs_fb_cb_tune() argument
10257 u32 dpll, fp, fp2; ilk_compute_dpll() local
12121 u32 dpll = pipe_config->dpll_hw_state.dpll; i9xx_pll_refclk() local
12140 u32 dpll = pipe_config->dpll_hw_state.dpll; i9xx_crtc_clock_get() local
18072 u32 dpll, fp; i830_enable_pipe() local
[all...]
/kernel/linux/linux-5.10/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c684 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
690 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
693 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
697 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
699 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
702 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
703 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1060 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1072 dpll in intelfbhw_mode_to_hw()
1281 const u32 *dpll, *fp0, *fp1, *pipe_conf; intelfbhw_program_mode() local
[all...]
/kernel/linux/linux-6.6/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1043 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1058 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1070 dpll in intelfbhw_mode_to_hw()
1279 const u32 *dpll, *fp0, *fp1, *pipe_conf; intelfbhw_program_mode() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
H A Drcar_du_crtc.c85 struct dpll_info *dpll, in rcar_du_dpll_divider()
149 dpll->n = n; in rcar_du_dpll_divider()
150 dpll->m = m; in rcar_du_dpll_divider()
151 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
152 dpll->output = output; in rcar_du_dpll_divider()
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
224 struct dpll_info dpll in rcar_du_crtc_set_display_timing() local
84 rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc, struct dpll_info *dpll, unsigned long input, unsigned long target) rcar_du_dpll_divider() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c83 struct dpll_info *dpll, in rcar_du_dpll_divider()
147 dpll->n = n; in rcar_du_dpll_divider()
148 dpll->m = m; in rcar_du_dpll_divider()
149 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
150 dpll->output = output; in rcar_du_dpll_divider()
162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
217 struct dpll_info dpll in rcar_du_crtc_set_display_timing() local
82 rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc, struct dpll_info *dpll, unsigned long input, unsigned long target) rcar_du_dpll_divider() argument
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/kernel/linux/linux-5.10/drivers/ata/
H A Dpata_hpt3x2n.c317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
/kernel/linux/linux-6.6/drivers/ata/
H A Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()

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