Lines Matching refs:dpll
242 temp = REG_READ_WITH_AUX(map->dpll, i);
244 REG_WRITE_WITH_AUX(map->dpll, temp, i);
245 REG_READ_WITH_AUX(map->dpll, i);
248 REG_WRITE_WITH_AUX(map->dpll,
250 REG_READ_WITH_AUX(map->dpll, i);
253 REG_WRITE_WITH_AUX(map->dpll,
255 REG_READ_WITH_AUX(map->dpll, i);
314 temp = REG_READ_WITH_AUX(map->dpll, i);
316 REG_WRITE_WITH_AUX(map->dpll,
318 REG_READ_WITH_AUX(map->dpll, i);
370 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
499 dpll = 0; /*BIT16 = 0 for 100MHz reference */
523 dpll |= DPLL_VGA_MODE_DIS;
526 dpll |= DPLL_VCO_ENABLE;
529 dpll |= DPLLA_MODE_LVDS;
531 dpll |= DPLLB_MODE_DAC_SERIAL;
537 dpll |= DPLL_DVO_HIGH_SPEED;
538 dpll |=
546 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
548 dpll |= (1 << (clock.p1 - 2)) << 17;
550 dpll |= DPLL_VCO_ENABLE;
552 if (dpll & DPLL_VCO_ENABLE) {
555 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
556 REG_READ_WITH_AUX(map->dpll, i);
564 REG_WRITE_WITH_AUX(map->dpll, dpll, i);
565 REG_READ_WITH_AUX(map->dpll, i);
570 REG_WRITE_WITH_AUX(map->dpll, dpll, i);
571 REG_READ_WITH_AUX(map->dpll, i);