Lines Matching refs:dpll
682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
688 if (dpll & DPLL_P1_FORCE_DIV2)
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
697 if (dpll & DPLL_P1_FORCE_DIV2)
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
1043 u32 *dpll, *fp0, *fp1;
1058 dpll = &hw->dpll_b;
1070 dpll = &hw->dpll_a;
1106 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1107 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1108 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1131 *dpll &= ~DPLL_P1_FORCE_DIV2;
1132 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1136 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1137 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1139 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1279 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1301 dpll = &hw->dpll_b;
1325 dpll = &hw->dpll_a;
1405 OUTREG(dpll_reg, *dpll);