18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * linux/arch/arm/plat-omap/sram-fn.S 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Functions that need to be run in internal SRAM 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#include <linux/linkage.h> 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <asm/assembler.h> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <mach/hardware.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#include "iomap.h" 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci .text 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci/* 198c2ecf20Sopenharmony_ci * Reprograms ULPD and CKCTL. 208c2ecf20Sopenharmony_ci */ 218c2ecf20Sopenharmony_ci .align 3 228c2ecf20Sopenharmony_ciENTRY(omap1_sram_reprogram_clock) 238c2ecf20Sopenharmony_ci stmfd sp!, {r0 - r12, lr} @ save registers on stack 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 268c2ecf20Sopenharmony_ci orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 278c2ecf20Sopenharmony_ci orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 308c2ecf20Sopenharmony_ci orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 318c2ecf20Sopenharmony_ci orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci tst r0, #1 << 4 @ want lock mode? 348c2ecf20Sopenharmony_ci beq newck @ nope 358c2ecf20Sopenharmony_ci bic r0, r0, #1 << 4 @ else clear lock bit 368c2ecf20Sopenharmony_ci strh r0, [r2] @ set dpll into bypass mode 378c2ecf20Sopenharmony_ci orr r0, r0, #1 << 4 @ set lock bit again 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_cinewck: 408c2ecf20Sopenharmony_ci strh r1, [r3] @ write new ckctl value 418c2ecf20Sopenharmony_ci strh r0, [r2] @ write new dpll value 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci mov r4, #0x0700 @ let the clocks settle 448c2ecf20Sopenharmony_ci orr r4, r4, #0x00ff 458c2ecf20Sopenharmony_cidelay: sub r4, r4, #1 468c2ecf20Sopenharmony_ci cmp r4, #0 478c2ecf20Sopenharmony_ci bne delay 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_cilock: ldrh r4, [r2], #0 @ read back dpll value 508c2ecf20Sopenharmony_ci tst r0, #1 << 4 @ want lock mode? 518c2ecf20Sopenharmony_ci beq out @ nope 528c2ecf20Sopenharmony_ci tst r4, #1 << 0 @ dpll rate locked? 538c2ecf20Sopenharmony_ci beq lock @ try again 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ciout: 568c2ecf20Sopenharmony_ci ldmfd sp!, {r0 - r12, pc} @ restore regs and return 578c2ecf20Sopenharmony_ciENTRY(omap1_sram_reprogram_clock_sz) 588c2ecf20Sopenharmony_ci .word . - omap1_sram_reprogram_clock 59