162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * linux/arch/arm/plat-omap/sram-fn.S 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Functions that need to be run in internal SRAM 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#include <linux/linkage.h> 962306a36Sopenharmony_ci#include <linux/soc/ti/omap1-io.h> 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <asm/assembler.h> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#include "hardware.h" 1462306a36Sopenharmony_ci#include "iomap.h" 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci .text 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* 1962306a36Sopenharmony_ci * Reprograms ULPD and CKCTL. 2062306a36Sopenharmony_ci */ 2162306a36Sopenharmony_ci .align 3 2262306a36Sopenharmony_ciENTRY(omap1_sram_reprogram_clock) 2362306a36Sopenharmony_ci stmfd sp!, {r0 - r12, lr} @ save registers on stack 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 2662306a36Sopenharmony_ci orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 2762306a36Sopenharmony_ci orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 3062306a36Sopenharmony_ci orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 3162306a36Sopenharmony_ci orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci tst r0, #1 << 4 @ want lock mode? 3462306a36Sopenharmony_ci beq newck @ nope 3562306a36Sopenharmony_ci bic r0, r0, #1 << 4 @ else clear lock bit 3662306a36Sopenharmony_ci strh r0, [r2] @ set dpll into bypass mode 3762306a36Sopenharmony_ci orr r0, r0, #1 << 4 @ set lock bit again 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_cinewck: 4062306a36Sopenharmony_ci strh r1, [r3] @ write new ckctl value 4162306a36Sopenharmony_ci strh r0, [r2] @ write new dpll value 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci mov r4, #0x0700 @ let the clocks settle 4462306a36Sopenharmony_ci orr r4, r4, #0x00ff 4562306a36Sopenharmony_cidelay: sub r4, r4, #1 4662306a36Sopenharmony_ci cmp r4, #0 4762306a36Sopenharmony_ci bne delay 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_cilock: ldrh r4, [r2], #0 @ read back dpll value 5062306a36Sopenharmony_ci tst r0, #1 << 4 @ want lock mode? 5162306a36Sopenharmony_ci beq out @ nope 5262306a36Sopenharmony_ci tst r4, #1 << 0 @ dpll rate locked? 5362306a36Sopenharmony_ci beq lock @ try again 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciout: 5662306a36Sopenharmony_ci ldmfd sp!, {r0 - r12, pc} @ restore regs and return 5762306a36Sopenharmony_ciENTRY(omap1_sram_reprogram_clock_sz) 5862306a36Sopenharmony_ci .word . - omap1_sram_reprogram_clock 59