| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| H A D | dw_mmc-exynos.c | 133 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
137 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
139 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
145 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
147 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
156 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
205 u32 clksel; in dw_mci_exynos_resume_noirq() local
214 clksel in dw_mci_exynos_resume_noirq()
300 u32 timing = ios->timing, clksel; dw_mci_exynos_set_ios() local
405 u32 clksel; dw_mci_exynos_set_clksmpl() local
424 u32 clksel; dw_mci_exynos_move_next_clksmpl() local
[all...] |
| H A D | dw_mmc-zx.c | 38 unsigned int clksel; in dw_mci_zx_emmc_set_delay() local
54 ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel); in dw_mci_zx_emmc_set_delay()
59 clksel &= ~CLK_SAMP_DELAY_MASK; in dw_mci_zx_emmc_set_delay()
60 clksel |= CLK_SAMP_DELAY(delay); in dw_mci_zx_emmc_set_delay()
62 clksel &= ~READ_DQS_DELAY_MASK; in dw_mci_zx_emmc_set_delay()
63 clksel |= READ_DQS_DELAY(delay); in dw_mci_zx_emmc_set_delay()
66 regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel); in dw_mci_zx_emmc_set_delay()
74 ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel); in dw_mci_zx_emmc_set_delay()
78 } while (--loop && !(clksel & ZX_DLL_LOCKED)); in dw_mci_zx_emmc_set_delay()
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| H A D | dw_mmc-exynos.c | 143 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
148 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
150 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
152 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
157 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
159 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
168 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
217 u32 clksel; in dw_mci_exynos_resume_noirq() local
227 clksel in dw_mci_exynos_resume_noirq()
315 u32 timing = ios->timing, clksel; dw_mci_exynos_set_ios() local
421 u32 clksel; dw_mci_exynos_set_clksmpl() local
442 u32 clksel; dw_mci_exynos_move_next_clksmpl() local
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| H A D | clk-cpu.c | 105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
107 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
111 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
123 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; in rockchip_cpuclk_set_pre_muxs() local
125 if (!clksel->reg) in rockchip_cpuclk_set_pre_muxs()
129 __func__, clksel->reg, clksel in rockchip_cpuclk_set_pre_muxs()
141 const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; rockchip_cpuclk_set_post_muxs() local
[all...] |
| /kernel/linux/linux-5.10/drivers/clocksource/ |
| H A D | timer-cadence-ttc.c | 475 int clksel, ret; in ttc_timer_probe() local
503 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
504 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
505 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
511 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
512 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
513 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| H A D | timer-cadence-ttc.c | 476 int clksel, ret; in ttc_timer_probe() local
504 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
505 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
506 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
512 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
513 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
514 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| H A D | clk-cpu.c | 109 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
111 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
115 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
116 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
|
| /kernel/linux/linux-5.10/arch/mips/ralink/ |
| H A D | rt3883.c | 67 u32 clksel; in ralink_clk_init() local
71 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & in ralink_clk_init()
75 switch (clksel) { in ralink_clk_init()
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| /kernel/linux/linux-6.6/arch/arm/mach-imx/ |
| H A D | mach-imx6q.c | 85 u32 clksel; in imx6q_1588_init() local
118 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
125 clksel); in imx6q_1588_init()
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| /kernel/linux/linux-5.10/drivers/clk/ |
| H A D | clk-qoriq.c | 57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
827 u32 clksel; in mux_set_parent() local
832 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
841 u32 clksel; in mux_get_parent() local
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
846 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
848 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
877 pll = hwc->info->clksel[id in get_pll_div()
950 u32 clksel; create_one_cmux() local
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/ |
| H A D | clk-qoriq.c | 59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
852 u32 clksel; in mux_set_parent() local
857 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
866 u32 clksel; in mux_get_parent() local
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
871 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
873 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
900 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
903 pll = hwc->info->clksel[id in get_pll_div()
976 u32 clksel; create_one_cmux() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/zte/ |
| H A D | zx_vou.c | 138 u32 clksel; member
145 .clksel = VOU_CLK_GL0_SEL,
149 .clksel = VOU_CLK_GL1_SEL,
157 .clksel = VOU_CLK_VL0_SEL,
161 .clksel = VOU_CLK_VL1_SEL,
165 .clksel = VOU_CLK_VL2_SEL,
618 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0); in zx_vou_layer_enable()
622 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, in zx_vou_layer_enable()
623 bits->clksel); in zx_vou_layer_enable()
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| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| H A D | mach-imx6q.c | 170 u32 clksel; in imx6q_1588_init() local
195 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
202 clksel); in imx6q_1588_init()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/ |
| H A D | rcar_lvds.c | 192 u32 clksel; member
197 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc()
305 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
339 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in __rcar_lvds_pll_setup_d3_e3()
195 rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, unsigned long target, struct pll_info *pll, u32 clksel, bool dot_clock_only) rcar_lvds_d3_e3_pll_calc() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_lvds.c | 138 u32 clksel; member
143 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc()
251 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
285 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in rcar_lvds_pll_setup_d3_e3()
141 rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, unsigned long target, struct pll_info *pll, u32 clksel, bool dot_clock_only) rcar_lvds_d3_e3_pll_calc() argument
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| H A D | asic3.c | 387 unsigned long clksel = 0; in asic3_irq_probe() local
397 clksel |= CLOCK_SEL_CX; in asic3_irq_probe()
399 clksel); in asic3_irq_probe()
961 unsigned long clksel; in asic3_probe() local
990 clksel = 0; in asic3_probe()
991 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
|