Lines Matching refs:clksel
59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
852 u32 clksel;
857 clksel = hwc->parent_to_clksel[idx];
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
866 u32 clksel;
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
871 ret = hwc->clksel_to_parent[clksel];
873 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
900 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
903 pll = hwc->info->clksel[idx].pll;
904 div = hwc->info->clksel[idx].div;
937 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
976 u32 clksel;
990 * Find the rate for the default clksel, and treat it as the
993 * default clksel) may be inappropriately excluded on certain
996 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
997 div = get_pll_div(cg, hwc, clksel);