Lines Matching refs:clksel
57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
827 u32 clksel;
832 clksel = hwc->parent_to_clksel[idx];
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
841 u32 clksel;
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
846 ret = hwc->clksel_to_parent[clksel];
848 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
877 pll = hwc->info->clksel[idx].pll;
878 div = hwc->info->clksel[idx].div;
911 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
950 u32 clksel;
964 * Find the rate for the default clksel, and treat it as the
967 * default clksel) may be inappropriately excluded on certain
970 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
971 div = get_pll_div(cg, hwc, clksel);