Home
last modified time | relevance | path

Searched refs:RREG32_NO_KIQ (Results 1 - 25 of 35) sorted by relevance

12

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c323 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
337 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
345 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
356 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
372 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
377 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
393 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
403 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
502 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNT in xgpu_vi_set_mailbox_ack_irq()
[all...]
H A Dmxgpu_ai.c56 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
138 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
180 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
227 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
275 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
H A Dmxgpu_nv.c55 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_peek_msg()
64 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_rcv_msg()
183 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); in xgpu_nv_send_access_requests()
194 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); in xgpu_nv_send_access_requests()
245 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_ack_irq()
299 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_rcv_irq()
H A Dvega10_ih.c396 wptr = RREG32_NO_KIQ(reg); in vega10_ih_get_wptr()
421 tmp = RREG32_NO_KIQ(reg); in vega10_ih_get_wptr()
496 v = RREG32_NO_KIQ(reg_rptr); in vega10_ih_irq_rearm()
H A Dvi.c92 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_rreg()
93 r = RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_rreg()
104 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_wreg()
106 (void)RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_wreg()
117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
H A Dgmc_v10_0.c217 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + in gmc_v10_0_flush_vm_hub()
235 RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); in gmc_v10_0_flush_vm_hub()
239 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + in gmc_v10_0_flush_vm_hub()
H A Dnavi10_ih.c468 wptr = RREG32_NO_KIQ(reg); in navi10_ih_get_wptr()
492 tmp = RREG32_NO_KIQ(reg); in navi10_ih_get_wptr()
566 v = RREG32_NO_KIQ(reg_rptr); in navi10_ih_irq_rearm()
H A Dsoc15_common.h39 RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
H A Dgmc_v9_0.c772 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + in gmc_v9_0_flush_gpu_tlb()
793 RREG32_NO_KIQ(hub->vm_inv_eng0_req + in gmc_v9_0_flush_gpu_tlb()
797 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + in gmc_v9_0_flush_gpu_tlb()
H A Damdgpu_virt.c45 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
H A Damdgpu.h1060 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
H A Damdgpu_ttm.c1671 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_access_memory()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c325 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
330 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
339 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
347 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
358 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
374 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
379 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
395 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
405 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
504 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNT in xgpu_vi_set_mailbox_ack_irq()
[all...]
H A Dmxgpu_ai.c58 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
68 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
140 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
182 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
303 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
H A Dmxgpu_nv.c57 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_rcv_msg()
191 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); in xgpu_nv_send_access_requests()
202 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); in xgpu_nv_send_access_requests()
262 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_ack_irq()
328 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_rcv_irq()
H A Dvega10_ih.c356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
372 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega10_ih_get_wptr()
403 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega10_ih_irq_rearm()
H A Dih_v6_0.c403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_0_get_wptr()
449 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_0_irq_rearm()
H A Dih_v6_1.c403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_1_get_wptr()
418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_1_get_wptr()
450 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_1_irq_rearm()
H A Dnavi10_ih.c427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in navi10_ih_get_wptr()
442 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in navi10_ih_get_wptr()
473 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in navi10_ih_irq_rearm()
H A Dvega20_ih.c404 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
420 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega20_ih_get_wptr()
452 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega20_ih_irq_rearm()
H A Dvi.c305 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_rreg()
306 r = RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_rreg()
317 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_wreg()
319 (void)RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_wreg()
330 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
H A Dgmc_v11_0.c258 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); in gmc_v11_0_flush_vm_hub()
264 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); in gmc_v11_0_flush_vm_hub()
H A Damdgpu_virt.c50 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
1092 return RREG32_NO_KIQ(offset); in amdgpu_sriov_rreg()
H A Damdgpu.h1163 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
H A Dgmc_v9_0.c898 RREG32_NO_KIQ(hub->vm_inv_eng0_req + in gmc_v9_0_flush_gpu_tlb()

Completed in 31 milliseconds

12