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Searched refs:DISP_CC_MDSS_CORE_BCR (Results 1 - 25 of 27) sorted by relevance

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/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm6375-dispcc.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8150.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8350.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sc8280xp.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8550-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8450-dispcc.h95 #define DISP_CC_MDSS_CORE_BCR 0 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm6375-dispcc.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8150.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8350.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sc8280xp.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8450-dispcc.h95 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8550-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dqcom,dispcc-sm8150.h60 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h60 #define DISP_CC_MDSS_CORE_BCR 0 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dqcom,dispcc-sm8150.h60 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h60 #define DISP_CC_MDSS_CORE_BCR 0 macro
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Ddispcc-qcm2290.c449 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
H A Ddispcc-sm6375.c544 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
H A Ddispcc-sm8250.c1219 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
H A Ddispcc-sm8550.c1724 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Ddispcc-sm8250.c1020 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },

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