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/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dmt6359.h140 #define RG_LDO_VAUD18_EN_MASK 0x1
141 #define RG_LDO_VAUD18_EN_MASK_SFT (0x1 << 0)
145 #define RG_VOW13M_CK_PDN_MASK 0x1
146 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
148 #define RG_VOW32K_CK_PDN_MASK 0x1
149 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
151 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
152 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
154 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
155 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 <<
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H A Drt5631.h83 #define RT5631_L_MUTE (0x1 << 15)
85 #define RT5631_L_EN (0x1 << 14)
87 #define RT5631_R_MUTE (0x1 << 7)
89 #define RT5631_R_EN (0x1 << 6)
96 #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14)
98 #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14)
99 #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6)
101 #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6)
104 #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14)
106 #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 1
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H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 <<
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H A Drt5645.h219 #define RT5645_L_MUTE (0x1 << 15)
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
223 #define RT5645_R_MUTE (0x1 << 7)
225 #define RT5645_VOL_R_MUTE (0x1 << 6)
235 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
238 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
239 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
240 #define RT5645_CBJ_MIC_SW (0x1 <<
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H A Drt5651.h176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 <<
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H A Drt5640.h182 #define RT5640_L_MUTE (0x1 << 15)
184 #define RT5640_VOL_L_MUTE (0x1 << 14)
186 #define RT5640_R_MUTE (0x1 << 7)
188 #define RT5640_VOL_R_MUTE (0x1 << 6)
206 #define RT5640_IN_DF1 (0x1 << 7)
208 #define RT5640_IN_DF2 (0x1 << 6)
212 #define RT5640_INL_SEL_MASK (0x1 << 15)
215 #define RT5640_INL_SEL_MONOP (0x1 << 15)
218 #define RT5640_INR_SEL_MASK (0x1 << 7)
221 #define RT5640_INR_SEL_MONON (0x1 <<
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H A Drt5660.h133 #define RT5660_L_MUTE (0x1 << 15)
135 #define RT5660_VOL_L_MUTE (0x1 << 14)
137 #define RT5660_R_MUTE (0x1 << 7)
139 #define RT5660_VOL_R_MUTE (0x1 << 6)
147 #define RT5660_IN_DF1 (0x1 << 15)
151 #define RT5660_IN_DF2 (0x1 << 7)
157 #define RT5660_IN_DF3 (0x1 << 15)
161 #define RT5660_IN_DF4 (0x1 << 7)
185 #define RT5660_M_ADC_L1 (0x1 << 14)
187 #define RT5660_M_ADC_L2 (0x1 << 1
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H A Drt5670.h213 #define RT5670_L_MUTE (0x1 << 15)
215 #define RT5670_VOL_L_MUTE (0x1 << 14)
217 #define RT5670_R_MUTE (0x1 << 7)
219 #define RT5670_VOL_R_MUTE (0x1 << 6)
229 #define RT5670_ID_5672 (0x1 << 1)
235 #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5670_CBJ_BST1_EN (0x1 << 2)
240 #define RT5670_CBJ_MN_JD (0x1 << 12)
241 #define RT5670_CAPLESS_EN (0x1 << 1
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/kernel/linux/linux-6.6/sound/soc/codecs/
H A Drt5631.h83 #define RT5631_L_MUTE (0x1 << 15)
85 #define RT5631_L_EN (0x1 << 14)
87 #define RT5631_R_MUTE (0x1 << 7)
89 #define RT5631_R_EN (0x1 << 6)
96 #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14)
98 #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14)
99 #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6)
101 #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6)
104 #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14)
106 #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 1
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H A Dmt6359.h140 #define AUXADC_RQST_CH0_MASK 0x1
141 #define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)
145 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
146 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)
151 #define AUXADC_ACCDET_AUTO_SPL_MASK 0x1
152 #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)
156 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
157 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)
172 #define RG_ACCDET_CK_PDN_MASK 0x1
173 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 <<
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H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 <<
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H A Drt5645.h217 #define RT5645_L_MUTE (0x1 << 15)
219 #define RT5645_VOL_L_MUTE (0x1 << 14)
221 #define RT5645_R_MUTE (0x1 << 7)
223 #define RT5645_VOL_R_MUTE (0x1 << 6)
233 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
234 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
235 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
236 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
237 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
238 #define RT5645_CBJ_MIC_SW (0x1 <<
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H A Drt5640.h183 #define RT5640_L_MUTE (0x1 << 15)
185 #define RT5640_VOL_L_MUTE (0x1 << 14)
187 #define RT5640_R_MUTE (0x1 << 7)
189 #define RT5640_VOL_R_MUTE (0x1 << 6)
207 #define RT5640_IN_DF1 (0x1 << 7)
209 #define RT5640_IN_DF2 (0x1 << 6)
213 #define RT5640_INL_SEL_MASK (0x1 << 15)
216 #define RT5640_INL_SEL_MONOP (0x1 << 15)
219 #define RT5640_INR_SEL_MASK (0x1 << 7)
222 #define RT5640_INR_SEL_MONON (0x1 <<
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H A Drt5651.h176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 <<
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H A Drt5660.h133 #define RT5660_L_MUTE (0x1 << 15)
135 #define RT5660_VOL_L_MUTE (0x1 << 14)
137 #define RT5660_R_MUTE (0x1 << 7)
139 #define RT5660_VOL_R_MUTE (0x1 << 6)
147 #define RT5660_IN_DF1 (0x1 << 15)
151 #define RT5660_IN_DF2 (0x1 << 7)
157 #define RT5660_IN_DF3 (0x1 << 15)
161 #define RT5660_IN_DF4 (0x1 << 7)
185 #define RT5660_M_ADC_L1 (0x1 << 14)
187 #define RT5660_M_ADC_L2 (0x1 << 1
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H A Drt5677.h298 #define RT5677_L_MUTE (0x1 << 15)
300 #define RT5677_VOL_L_MUTE (0x1 << 14)
302 #define RT5677_R_MUTE (0x1 << 7)
304 #define RT5677_VOL_R_MUTE (0x1 << 6)
312 #define RT5677_LOUT1_L_MUTE (0x1 << 15)
314 #define RT5677_LOUT1_L_DF (0x1 << 14)
316 #define RT5677_LOUT2_L_MUTE (0x1 << 13)
318 #define RT5677_LOUT2_L_DF (0x1 << 12)
320 #define RT5677_LOUT3_L_MUTE (0x1 << 11)
322 #define RT5677_LOUT3_L_DF (0x1 << 1
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/kernel/linux/linux-6.6/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 2
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/kernel/linux/linux-5.10/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 2
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/kernel/linux/linux-6.6/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 2
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/kernel/linux/linux-5.10/drivers/infiniband/hw/qib/
H A Dqib_7220_regs.h39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
61 #define QIB_7220_Control_Reserved_RMASK 0x1
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
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/kernel/linux/linux-6.6/drivers/infiniband/hw/qib/
H A Dqib_7220_regs.h39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
61 #define QIB_7220_Control_Reserved_RMASK 0x1
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
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/kernel/linux/linux-5.10/drivers/soc/samsung/
H A Dexynos3250-pmu.c21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
26 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
27 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
28 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
29 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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/kernel/linux/linux-6.6/drivers/soc/samsung/
H A Dexynos3250-pmu.c21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
26 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
27 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
28 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
29 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.h123 #define RESET_DP_TX (0x1 << 0)
126 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
127 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
128 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
129 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
130 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
131 #define AUD_FUNC_EN_N (0x1 << 3)
132 #define HDCP_FUNC_EN_N (0x1 << 2)
133 #define CRC_FUNC_EN_N (0x1 << 1)
134 #define SW_FUNC_EN_N (0x1 <<
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/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.h123 #define RESET_DP_TX (0x1 << 0)
126 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
127 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
128 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
129 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
130 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
131 #define AUD_FUNC_EN_N (0x1 << 3)
132 #define HDCP_FUNC_EN_N (0x1 << 2)
133 #define CRC_FUNC_EN_N (0x1 << 1)
134 #define SW_FUNC_EN_N (0x1 <<
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