Lines Matching refs:x1
213 #define RT5670_L_MUTE (0x1 << 15)
215 #define RT5670_VOL_L_MUTE (0x1 << 14)
217 #define RT5670_R_MUTE (0x1 << 7)
219 #define RT5670_VOL_R_MUTE (0x1 << 6)
229 #define RT5670_ID_5672 (0x1 << 1)
235 #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5670_CBJ_BST1_EN (0x1 << 2)
240 #define RT5670_CBJ_MN_JD (0x1 << 12)
241 #define RT5670_CAPLESS_EN (0x1 << 11)
242 #define RT5670_CBJ_DET_MODE (0x1 << 7)
249 #define RT5670_IN_DF1 (0x1 << 7)
251 #define RT5670_IN_DF2 (0x1 << 6)
255 #define RT5670_INL_SEL_MASK (0x1 << 15)
258 #define RT5670_INL_SEL_MONOP (0x1 << 15)
261 #define RT5670_INR_SEL_MASK (0x1 << 7)
264 #define RT5670_INR_SEL_MONON (0x1 << 7)
271 #define RT5670_M_ST_DACR2 (0x1 << 8)
273 #define RT5670_M_ST_DACL2 (0x1 << 7)
275 #define RT5670_ST_EN (0x1 << 6)
291 #define RT5670_M_DAC_L2_VOL (0x1 << 13)
293 #define RT5670_M_DAC_R2_VOL (0x1 << 12)
327 #define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
331 #define RT5670_M_ADC_L1 (0x1 << 14)
333 #define RT5670_M_ADC_L2 (0x1 << 13)
335 #define RT5670_ADC_1_SRC_MASK (0x1 << 12)
337 #define RT5670_ADC_1_SRC_ADC (0x1 << 12)
339 #define RT5670_ADC_2_SRC_MASK (0x1 << 11)
341 #define RT5670_ADC_SRC_MASK (0x1 << 10)
345 #define RT5670_M_ADC_R1 (0x1 << 6)
347 #define RT5670_M_ADC_R2 (0x1 << 5)
349 #define RT5670_DMIC3_SRC_MASK (0x1 << 1)
353 #define RT5670_M_MONO_ADC_L1 (0x1 << 14)
355 #define RT5670_M_MONO_ADC_L2 (0x1 << 13)
357 #define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
360 #define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
361 #define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
363 #define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
367 #define RT5670_M_MONO_ADC_R1 (0x1 << 6)
369 #define RT5670_M_MONO_ADC_R2 (0x1 << 5)
371 #define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
373 #define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
375 #define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
381 #define RT5670_M_ADCMIX_L (0x1 << 15)
383 #define RT5670_M_DAC1_L (0x1 << 14)
388 #define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
394 #define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
397 #define RT5670_M_ADCMIX_R (0x1 << 7)
399 #define RT5670_M_DAC1_R (0x1 << 6)
403 #define RT5670_M_DAC_L1 (0x1 << 14)
405 #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
407 #define RT5670_M_DAC_L2 (0x1 << 12)
409 #define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
411 #define RT5670_M_DAC_R1_STO_L (0x1 << 9)
413 #define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
415 #define RT5670_M_DAC_R1 (0x1 << 6)
417 #define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
419 #define RT5670_M_DAC_R2 (0x1 << 4)
421 #define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
423 #define RT5670_M_DAC_L1_STO_R (0x1 << 1)
425 #define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
429 #define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
431 #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
433 #define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
435 #define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
437 #define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
439 #define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
441 #define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
443 #define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
445 #define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
447 #define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
449 #define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
451 #define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
455 #define RT5670_M_STO_L_DAC_L (0x1 << 15)
457 #define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
459 #define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
461 #define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
463 #define RT5670_M_STO_R_DAC_R (0x1 << 11)
465 #define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
467 #define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
469 #define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
471 #define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
473 #define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
475 #define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
477 #define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
486 #define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
491 #define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
495 #define RT5670_DSP_UL_SEL (0x1 << 1)
497 #define RT5670_DSP_DL_SEL 0x1
507 #define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
521 #define RT5670_PDM1_L_MASK (0x1 << 15)
523 #define RT5670_M_PDM1_L (0x1 << 14)
525 #define RT5670_PDM1_R_MASK (0x1 << 13)
527 #define RT5670_M_PDM1_R (0x1 << 12)
529 #define RT5670_PDM2_L_MASK (0x1 << 11)
531 #define RT5670_M_PDM2_L (0x1 << 10)
533 #define RT5670_PDM2_R_MASK (0x1 << 9)
535 #define RT5670_M_PDM2_R (0x1 << 8)
537 #define RT5670_PDM2_BUSY (0x1 << 7)
538 #define RT5670_PDM1_BUSY (0x1 << 6)
539 #define RT5670_PDM_PATTERN (0x1 << 5)
540 #define RT5670_PDM_GAIN (0x1 << 4)
558 #define RT5670_M_IN_L_RM_L (0x1 << 5)
560 #define RT5670_M_BST2_RM_L (0x1 << 3)
562 #define RT5670_M_BST1_RM_L (0x1 << 1)
580 #define RT5670_M_IN_R_RM_R (0x1 << 5)
582 #define RT5670_M_BST2_RM_R (0x1 << 3)
584 #define RT5670_M_BST1_RM_R (0x1 << 1)
588 #define RT5670_M_DAC2_HM (0x1 << 15)
590 #define RT5670_M_HPVOL_HM (0x1 << 14)
592 #define RT5670_M_DAC1_HM (0x1 << 13)
594 #define RT5670_G_HPOMIX_MASK (0x1 << 12)
596 #define RT5670_M_INR1_HMR (0x1 << 3)
598 #define RT5670_M_DACR1_HMR (0x1 << 2)
600 #define RT5670_M_INL1_HML (0x1 << 1)
602 #define RT5670_M_DACL1_HML (0x1)
606 #define RT5670_M_DAC_R2_MA (0x1 << 15)
608 #define RT5670_M_DAC_L2_MA (0x1 << 14)
610 #define RT5670_M_OV_R_MM (0x1 << 13)
612 #define RT5670_M_OV_L_MM (0x1 << 12)
614 #define RT5670_G_MONOMIX_MASK (0x1 << 10)
616 #define RT5670_M_DAC_R2_MM (0x1 << 9)
618 #define RT5670_M_DAC_L2_MM (0x1 << 8)
620 #define RT5670_M_BST4_MM (0x1 << 7)
644 #define RT5670_M_BST1_OM_L (0x1 << 5)
646 #define RT5670_M_IN_L_OM_L (0x1 << 4)
648 #define RT5670_M_DAC_L2_OM_L (0x1 << 1)
650 #define RT5670_M_DAC_L1_OM_L (0x1)
674 #define RT5670_M_BST2_OM_R (0x1 << 6)
676 #define RT5670_M_IN_R_OM_R (0x1 << 4)
678 #define RT5670_M_DAC_R2_OM_R (0x1 << 1)
680 #define RT5670_M_DAC_R1_OM_R (0x1)
684 #define RT5670_M_DAC_L1_LM (0x1 << 15)
686 #define RT5670_M_DAC_R1_LM (0x1 << 14)
688 #define RT5670_M_OV_L_LM (0x1 << 13)
690 #define RT5670_M_OV_R_LM (0x1 << 12)
692 #define RT5670_G_LOUTMIX_MASK (0x1 << 11)
696 #define RT5670_PWR_I2S1 (0x1 << 15)
698 #define RT5670_PWR_I2S2 (0x1 << 14)
700 #define RT5670_PWR_DAC_L1 (0x1 << 12)
702 #define RT5670_PWR_DAC_R1 (0x1 << 11)
704 #define RT5670_PWR_DAC_L2 (0x1 << 7)
706 #define RT5670_PWR_DAC_R2 (0x1 << 6)
708 #define RT5670_PWR_ADC_L (0x1 << 2)
710 #define RT5670_PWR_ADC_R (0x1 << 1)
712 #define RT5670_PWR_CLS_D (0x1)
716 #define RT5670_PWR_ADC_S1F (0x1 << 15)
718 #define RT5670_PWR_ADC_MF_L (0x1 << 14)
720 #define RT5670_PWR_ADC_MF_R (0x1 << 13)
722 #define RT5670_PWR_I2S_DSP (0x1 << 12)
724 #define RT5670_PWR_DAC_S1F (0x1 << 11)
726 #define RT5670_PWR_DAC_MF_L (0x1 << 10)
728 #define RT5670_PWR_DAC_MF_R (0x1 << 9)
730 #define RT5670_PWR_ADC_S2F (0x1 << 8)
732 #define RT5670_PWR_PDM1 (0x1 << 7)
734 #define RT5670_PWR_PDM2 (0x1 << 6)
738 #define RT5670_PWR_VREF1 (0x1 << 15)
740 #define RT5670_PWR_FV1 (0x1 << 14)
742 #define RT5670_PWR_MB (0x1 << 13)
744 #define RT5670_PWR_LM (0x1 << 12)
746 #define RT5670_PWR_BG (0x1 << 11)
748 #define RT5670_PWR_HP_L (0x1 << 7)
750 #define RT5670_PWR_HP_R (0x1 << 6)
752 #define RT5670_PWR_HA (0x1 << 5)
754 #define RT5670_PWR_VREF2 (0x1 << 4)
756 #define RT5670_PWR_FV2 (0x1 << 3)
762 #define RT5670_PWR_BST1 (0x1 << 15)
764 #define RT5670_PWR_BST2 (0x1 << 13)
766 #define RT5670_PWR_MB1 (0x1 << 11)
768 #define RT5670_PWR_MB2 (0x1 << 10)
770 #define RT5670_PWR_PLL (0x1 << 9)
772 #define RT5670_PWR_BST1_P (0x1 << 6)
774 #define RT5670_PWR_BST2_P (0x1 << 4)
776 #define RT5670_PWR_JD1 (0x1 << 2)
778 #define RT5670_PWR_JD (0x1 << 1)
782 #define RT5670_PWR_OM_L (0x1 << 15)
784 #define RT5670_PWR_OM_R (0x1 << 14)
786 #define RT5670_PWR_RM_L (0x1 << 11)
788 #define RT5670_PWR_RM_R (0x1 << 10)
792 #define RT5670_PWR_HV_L (0x1 << 11)
794 #define RT5670_PWR_HV_R (0x1 << 10)
796 #define RT5670_PWR_IN_L (0x1 << 9)
798 #define RT5670_PWR_IN_R (0x1 << 8)
800 #define RT5670_PWR_MIC_DET (0x1 << 5)
804 #define RT5670_I2S_MS_MASK (0x1 << 15)
807 #define RT5670_I2S_MS_S (0x1 << 15)
813 #define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
818 #define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
820 #define RT5670_I2S_BP_MASK (0x1 << 7)
823 #define RT5670_I2S_BP_INV (0x1 << 7)
827 #define RT5670_I2S_DL_20 (0x1 << 2)
833 #define RT5670_I2S_DF_LEFT (0x1)
838 #define RT5670_I2S2_SDI_MASK (0x1 << 6)
841 #define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
844 #define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
847 #define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
851 #define RT5670_I2S_PD1_2 (0x1 << 12)
858 #define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
861 #define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
865 #define RT5670_I2S_PD2_2 (0x1 << 8)
872 #define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
875 #define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
879 #define RT5670_I2S_PD3_2 (0x1 << 4)
889 #define RT5670_DAC_OSR_64 (0x1 << 2)
895 #define RT5670_ADC_OSR_64 (0x1)
903 #define RT5670_DAC_L_OSR_64 (0x1 << 14)
909 #define RT5670_ADC_R_OSR_64 (0x1 << 12)
912 #define RT5670_DAHPF_EN (0x1 << 11)
914 #define RT5670_ADHPF_EN (0x1 << 10)
918 #define RT5670_DMIC_1_EN_MASK (0x1 << 15)
921 #define RT5670_DMIC_1_EN (0x1 << 15)
922 #define RT5670_DMIC_2_EN_MASK (0x1 << 14)
925 #define RT5670_DMIC_2_EN (0x1 << 14)
926 #define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
929 #define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
930 #define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
933 #define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
934 #define RT5670_DMIC_2_DP_MASK (0x1 << 10)
937 #define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
938 #define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
941 #define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
942 #define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
945 #define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
948 #define RT5670_DMIC_3_EN_MASK (0x1 << 4)
951 #define RT5670_DMIC_3_EN (0x1 << 4)
955 #define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
962 #define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
969 #define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
974 #define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
977 #define RT5670_PLL1_PD_MASK (0x1 << 3)
980 #define RT5670_PLL1_PD_2 (0x1 << 3)
996 #define RT5670_PLL_M_BP (0x1 << 11)
1000 #define RT5670_STO_T_MASK (0x1 << 15)
1003 #define RT5670_STO_T_LRCK1 (0x1 << 15)
1004 #define RT5670_M1_T_MASK (0x1 << 14)
1007 #define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1008 #define RT5670_I2S2_F_MASK (0x1 << 12)
1011 #define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1012 #define RT5670_DMIC_1_M_MASK (0x1 << 9)
1015 #define RT5670_DMIC_1_M_ASYN (0x1 << 9)
1016 #define RT5670_DMIC_2_M_MASK (0x1 << 8)
1019 #define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1023 #define RT5670_CLK_SEL_I2S1_ASRC (0x1)
1056 #define RT5670_HP_OVCD_MASK (0x1 << 10)
1059 #define RT5670_HP_OVCD_EN (0x1 << 10)
1063 #define RT5670_HP_OC_TH_105 (0x1 << 8)
1068 #define RT5670_CLSD_OC_MASK (0x1 << 9)
1071 #define RT5670_CLSD_OC_PD (0x1 << 9)
1072 #define RT5670_AUTO_PD_MASK (0x1 << 8)
1075 #define RT5670_AUTO_PD_EN (0x1 << 8)
1082 #define RT5670_CLSD_OM_MASK (0x1 << 11)
1085 #define RT5670_CLSD_OM_STO (0x1 << 11)
1086 #define RT5670_CLSD_SCH_MASK (0x1 << 10)
1089 #define RT5670_CLSD_SCH_S (0x1 << 10)
1092 #define RT5670_SMT_TRIG_MASK (0x1 << 15)
1095 #define RT5670_SMT_TRIG_EN (0x1 << 15)
1096 #define RT5670_HP_L_SMT_MASK (0x1 << 9)
1099 #define RT5670_HP_L_SMT_EN (0x1 << 9)
1100 #define RT5670_HP_R_SMT_MASK (0x1 << 8)
1103 #define RT5670_HP_R_SMT_EN (0x1 << 8)
1104 #define RT5670_HP_CD_PD_MASK (0x1 << 7)
1107 #define RT5670_HP_CD_PD_EN (0x1 << 7)
1108 #define RT5670_RSTN_MASK (0x1 << 6)
1111 #define RT5670_RSTN_EN (0x1 << 6)
1112 #define RT5670_RSTP_MASK (0x1 << 5)
1115 #define RT5670_RSTP_EN (0x1 << 5)
1116 #define RT5670_HP_CO_MASK (0x1 << 4)
1119 #define RT5670_HP_CO_EN (0x1 << 4)
1120 #define RT5670_HP_CP_MASK (0x1 << 3)
1123 #define RT5670_HP_CP_PU (0x1 << 3)
1124 #define RT5670_HP_SG_MASK (0x1 << 2)
1127 #define RT5670_HP_SG_EN (0x1 << 2)
1128 #define RT5670_HP_DP_MASK (0x1 << 1)
1131 #define RT5670_HP_DP_PU (0x1 << 1)
1132 #define RT5670_HP_CB_MASK (0x1)
1135 #define RT5670_HP_CB_PU (0x1)
1138 #define RT5670_DEPOP_MASK (0x1 << 13)
1141 #define RT5670_DEPOP_MAN (0x1 << 13)
1142 #define RT5670_RAMP_MASK (0x1 << 12)
1145 #define RT5670_RAMP_EN (0x1 << 12)
1146 #define RT5670_BPS_MASK (0x1 << 11)
1149 #define RT5670_BPS_EN (0x1 << 11)
1150 #define RT5670_FAST_UPDN_MASK (0x1 << 10)
1153 #define RT5670_FAST_UPDN_EN (0x1 << 10)
1157 #define RT5670_MRES_25MO (0x1 << 8)
1160 #define RT5670_VLO_MASK (0x1 << 7)
1163 #define RT5670_VLO_32V (0x1 << 7)
1164 #define RT5670_DIG_DP_MASK (0x1 << 6)
1167 #define RT5670_DIG_DP_EN (0x1 << 6)
1190 #define RT5670_OSW_L_MASK (0x1 << 11)
1193 #define RT5670_OSW_L_EN (0x1 << 11)
1194 #define RT5670_OSW_R_MASK (0x1 << 10)
1197 #define RT5670_OSW_R_EN (0x1 << 10)
1201 #define RT5670_PM_HP_MV (0x1 << 8)
1206 #define RT5670_IB_HP_25IL (0x1 << 6)
1211 #define RT5670_PVDD_DET_MASK (0x1 << 15)
1214 #define RT5670_PVDD_DET_EN (0x1 << 15)
1215 #define RT5670_SPK_AG_MASK (0x1 << 14)
1218 #define RT5670_SPK_AG_EN (0x1 << 14)
1221 #define RT5670_MIC1_BS_MASK (0x1 << 15)
1224 #define RT5670_MIC1_BS_75AV (0x1 << 15)
1225 #define RT5670_MIC2_BS_MASK (0x1 << 14)
1228 #define RT5670_MIC2_BS_75AV (0x1 << 14)
1229 #define RT5670_MIC1_CLK_MASK (0x1 << 13)
1232 #define RT5670_MIC1_CLK_EN (0x1 << 13)
1233 #define RT5670_MIC2_CLK_MASK (0x1 << 12)
1236 #define RT5670_MIC2_CLK_EN (0x1 << 12)
1237 #define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1240 #define RT5670_MIC1_OVCD_EN (0x1 << 11)
1244 #define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
1246 #define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1249 #define RT5670_MIC2_OVCD_EN (0x1 << 8)
1253 #define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
1255 #define RT5670_PWR_MB_MASK (0x1 << 5)
1258 #define RT5670_PWR_MB_PU (0x1 << 5)
1259 #define RT5670_PWR_CLK25M_MASK (0x1 << 4)
1262 #define RT5670_PWR_CLK25M_PU (0x1 << 4)
1267 #define RT5670_JD1_MODE_1 (0x1 << 0)
1275 #define RT5670_EQ_SRC_MASK (0x1 << 15)
1278 #define RT5670_EQ_SRC_ADC (0x1 << 15)
1279 #define RT5670_EQ_UPD (0x1 << 14)
1281 #define RT5670_EQ_CD_MASK (0x1 << 13)
1284 #define RT5670_EQ_CD_EN (0x1 << 13)
1288 #define RT5670_EQ_DITH_LSB (0x1 << 8)
1293 #define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1296 #define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1297 #define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
1300 #define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
1301 #define RT5670_EQ_HPF2_MASK (0x1 << 6)
1304 #define RT5670_EQ_HPF2_EN (0x1 << 6)
1305 #define RT5670_EQ_HPF1_MASK (0x1 << 5)
1308 #define RT5670_EQ_HPF1_EN (0x1 << 5)
1309 #define RT5670_EQ_BPF4_MASK (0x1 << 4)
1312 #define RT5670_EQ_BPF4_EN (0x1 << 4)
1313 #define RT5670_EQ_BPF3_MASK (0x1 << 3)
1316 #define RT5670_EQ_BPF3_EN (0x1 << 3)
1317 #define RT5670_EQ_BPF2_MASK (0x1 << 2)
1320 #define RT5670_EQ_BPF2_EN (0x1 << 2)
1321 #define RT5670_EQ_BPF1_MASK (0x1 << 1)
1324 #define RT5670_EQ_BPF1_EN (0x1 << 1)
1325 #define RT5670_EQ_LPF_MASK (0x1)
1328 #define RT5670_EQ_LPF_EN (0x1)
1332 #define RT5670_MT_MASK (0x1 << 15)
1335 #define RT5670_MT_EN (0x1 << 15)
1338 #define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1341 #define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1342 #define RT5670_DRC_AGC_MASK (0x1 << 14)
1345 #define RT5670_DRC_AGC_EN (0x1 << 14)
1346 #define RT5670_DRC_AGC_UPD (0x1 << 13)
1352 #define RT5670_DRC_AGC_R_48K (0x1 << 5)
1364 #define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
1367 #define RT5670_DRC_AGC_CP_EN (0x1 << 7)
1371 #define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
1382 #define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
1385 #define RT5670_DRC_AGC_NG_EN (0x1 << 6)
1386 #define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
1389 #define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
1397 #define RT5670_JD_GPIO1 (0x1 << 13)
1403 #define RT5670_JD_HP_MASK (0x1 << 11)
1406 #define RT5670_JD_HP_EN (0x1 << 11)
1407 #define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1410 #define RT5670_JD_HP_TRG_HI (0x1 << 10)
1411 #define RT5670_JD_SPL_MASK (0x1 << 9)
1414 #define RT5670_JD_SPL_EN (0x1 << 9)
1415 #define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1418 #define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1419 #define RT5670_JD_SPR_MASK (0x1 << 7)
1422 #define RT5670_JD_SPR_EN (0x1 << 7)
1423 #define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
1426 #define RT5670_JD_SPR_TRG_HI (0x1 << 6)
1427 #define RT5670_JD_MO_MASK (0x1 << 5)
1430 #define RT5670_JD_MO_EN (0x1 << 5)
1431 #define RT5670_JD_MO_TRG_MASK (0x1 << 4)
1434 #define RT5670_JD_MO_TRG_HI (0x1 << 4)
1435 #define RT5670_JD_LO_MASK (0x1 << 3)
1438 #define RT5670_JD_LO_EN (0x1 << 3)
1439 #define RT5670_JD_LO_TRG_MASK (0x1 << 2)
1442 #define RT5670_JD_LO_TRG_HI (0x1 << 2)
1443 #define RT5670_JD1_IN4P_MASK (0x1 << 1)
1446 #define RT5670_JD1_IN4P_EN (0x1 << 1)
1447 #define RT5670_JD2_IN4N_MASK (0x1)
1450 #define RT5670_JD2_IN4N_EN (0x1)
1453 #define RT5670_IRQ_JD_MASK (0x1 << 15)
1456 #define RT5670_IRQ_JD_NOR (0x1 << 15)
1457 #define RT5670_IRQ_OT_MASK (0x1 << 14)
1460 #define RT5670_IRQ_OT_NOR (0x1 << 14)
1461 #define RT5670_JD_STKY_MASK (0x1 << 13)
1464 #define RT5670_JD_STKY_EN (0x1 << 13)
1465 #define RT5670_OT_STKY_MASK (0x1 << 12)
1468 #define RT5670_OT_STKY_EN (0x1 << 12)
1469 #define RT5670_JD_P_MASK (0x1 << 11)
1472 #define RT5670_JD_P_INV (0x1 << 11)
1473 #define RT5670_OT_P_MASK (0x1 << 10)
1476 #define RT5670_OT_P_INV (0x1 << 10)
1477 #define RT5670_JD1_1_EN_MASK (0x1 << 9)
1480 #define RT5670_JD1_1_EN (0x1 << 9)
1483 #define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1486 #define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1487 #define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1490 #define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1491 #define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1494 #define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1495 #define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1498 #define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1499 #define RT5670_MB1_OC_P_MASK (0x1 << 7)
1502 #define RT5670_MB1_OC_P_INV (0x1 << 7)
1503 #define RT5670_MB2_OC_P_MASK (0x1 << 6)
1506 #define RT5670_MB2_OC_P_INV (0x1 << 6)
1507 #define RT5670_MB1_OC_CLR (0x1 << 3)
1509 #define RT5670_MB2_OC_CLR (0x1 << 2)
1513 #define RT5670_GP1_PIN_MASK (0x1 << 15)
1516 #define RT5670_GP1_PIN_IRQ (0x1 << 15)
1517 #define RT5670_GP2_PIN_MASK (0x1 << 14)
1520 #define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1524 #define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1526 #define RT5670_GP4_PIN_MASK (0x1 << 11)
1529 #define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1530 #define RT5670_DP_SIG_MASK (0x1 << 10)
1533 #define RT5670_DP_SIG_AP (0x1 << 10)
1534 #define RT5670_GPIO_M_MASK (0x1 << 9)
1537 #define RT5670_GPIO_M_PH (0x1 << 9)
1538 #define RT5670_I2S2_PIN_MASK (0x1 << 8)
1541 #define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1542 #define RT5670_GP5_PIN_MASK (0x1 << 7)
1545 #define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
1546 #define RT5670_GP6_PIN_MASK (0x1 << 6)
1549 #define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
1553 #define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
1555 #define RT5670_GP8_PIN_MASK (0x1 << 3)
1558 #define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
1559 #define RT5670_GP9_PIN_MASK (0x1 << 2)
1562 #define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
1566 #define RT5670_GP10_PIN_DMIC3_SDA (0x1)
1570 #define RT5670_GP4_PF_MASK (0x1 << 11)
1573 #define RT5670_GP4_PF_OUT (0x1 << 11)
1574 #define RT5670_GP4_OUT_MASK (0x1 << 10)
1577 #define RT5670_GP4_OUT_HI (0x1 << 10)
1578 #define RT5670_GP4_P_MASK (0x1 << 9)
1581 #define RT5670_GP4_P_INV (0x1 << 9)
1582 #define RT5670_GP3_PF_MASK (0x1 << 8)
1585 #define RT5670_GP3_PF_OUT (0x1 << 8)
1586 #define RT5670_GP3_OUT_MASK (0x1 << 7)
1589 #define RT5670_GP3_OUT_HI (0x1 << 7)
1590 #define RT5670_GP3_P_MASK (0x1 << 6)
1593 #define RT5670_GP3_P_INV (0x1 << 6)
1594 #define RT5670_GP2_PF_MASK (0x1 << 5)
1597 #define RT5670_GP2_PF_OUT (0x1 << 5)
1598 #define RT5670_GP2_OUT_MASK (0x1 << 4)
1601 #define RT5670_GP2_OUT_HI (0x1 << 4)
1602 #define RT5670_GP2_P_MASK (0x1 << 3)
1605 #define RT5670_GP2_P_INV (0x1 << 3)
1606 #define RT5670_GP1_PF_MASK (0x1 << 2)
1609 #define RT5670_GP1_PF_OUT (0x1 << 2)
1610 #define RT5670_GP1_OUT_MASK (0x1 << 1)
1613 #define RT5670_GP1_OUT_HI (0x1 << 1)
1614 #define RT5670_GP1_P_MASK (0x1)
1617 #define RT5670_GP1_P_INV (0x1)
1624 #define RT5670_SCB_SWAP_MASK (0x1 << 15)
1627 #define RT5670_SCB_SWAP_EN (0x1 << 15)
1628 #define RT5670_SCB_MASK (0x1 << 14)
1631 #define RT5670_SCB_EN (0x1 << 14)
1634 #define RT5670_BB_MASK (0x1 << 15)
1637 #define RT5670_BB_EN (0x1 << 15)
1641 #define RT5670_BB_CT_B (0x1 << 12)
1644 #define RT5670_M_BB_L_MASK (0x1 << 9)
1646 #define RT5670_M_BB_R_MASK (0x1 << 8)
1648 #define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
1650 #define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
1656 #define RT5670_M_MP3_L_MASK (0x1 << 15)
1658 #define RT5670_M_MP3_R_MASK (0x1 << 14)
1660 #define RT5670_M_MP3_MASK (0x1 << 13)
1663 #define RT5670_M_MP3_EN (0x1 << 13)
1666 #define RT5670_MP3_HLP_MASK (0x1 << 7)
1669 #define RT5670_MP3_HLP_EN (0x1 << 7)
1670 #define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
1672 #define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
1676 #define RT5670_MP3_WT_MASK (0x1 << 13)
1679 #define RT5670_MP3_WT_1_2 (0x1 << 13)
1686 #define RT5670_3D_CF_MASK (0x1 << 15)
1689 #define RT5670_3D_CF_EN (0x1 << 15)
1690 #define RT5670_3D_HP_MASK (0x1 << 14)
1693 #define RT5670_3D_HP_EN (0x1 << 14)
1694 #define RT5670_3D_BT_MASK (0x1 << 13)
1697 #define RT5670_3D_BT_EN (0x1 << 13)
1700 #define RT5670_3D_HP_M_MASK (0x1 << 10)
1703 #define RT5670_3D_HP_M_FRO (0x1 << 10)
1704 #define RT5670_M_3D_HRTF_MASK (0x1 << 9)
1706 #define RT5670_M_3D_D2H_MASK (0x1 << 8)
1708 #define RT5670_M_3D_D2R_MASK (0x1 << 7)
1710 #define RT5670_M_3D_REVB_MASK (0x1 << 6)
1714 #define RT5670_2ND_HPF_MASK (0x1 << 15)
1717 #define RT5670_2ND_HPF_EN (0x1 << 15)
1720 #define RT5670_1ST_HPF_MASK (0x1 << 11)
1723 #define RT5670_1ST_HPF_EN (0x1 << 11)
1731 #define RT5670_ZD_F_ZC_IM (0x1 << 4)
1736 #define RT5670_SI_DAC_MASK (0x1 << 11)
1739 #define RT5670_SI_DAC_TEST (0x1 << 11)
1740 #define RT5670_DC_CAL_M_MASK (0x1 << 10)
1743 #define RT5670_DC_CAL_M_NOR (0x1 << 10)
1744 #define RT5670_DC_CAL_MASK (0x1 << 9)
1747 #define RT5670_DC_CAL_EN (0x1 << 9)
1750 #define RT5670_HPD_PS_MASK (0x1 << 5)
1753 #define RT5670_HPD_PS_EN (0x1 << 5)
1754 #define RT5670_CAL_M_MASK (0x1 << 4)
1757 #define RT5670_CAL_M_CAL (0x1 << 4)
1758 #define RT5670_CAL_MASK (0x1 << 3)
1761 #define RT5670_CAL_EN (0x1 << 3)
1762 #define RT5670_CAL_TEST_MASK (0x1 << 2)
1765 #define RT5670_CAL_TEST_EN (0x1 << 2)
1769 #define RT5670_CAL_P_CAL (0x1)
1773 #define RT5670_SV_MASK (0x1 << 15)
1776 #define RT5670_SV_EN (0x1 << 15)
1777 #define RT5670_SPO_SV_MASK (0x1 << 14)
1780 #define RT5670_SPO_SV_EN (0x1 << 14)
1781 #define RT5670_OUT_SV_MASK (0x1 << 13)
1784 #define RT5670_OUT_SV_EN (0x1 << 13)
1785 #define RT5670_HP_SV_MASK (0x1 << 12)
1788 #define RT5670_HP_SV_EN (0x1 << 12)
1789 #define RT5670_ZCD_DIG_MASK (0x1 << 11)
1792 #define RT5670_ZCD_DIG_EN (0x1 << 11)
1793 #define RT5670_ZCD_MASK (0x1 << 10)
1796 #define RT5670_ZCD_PU (0x1 << 10)
1799 #define RT5670_M_ZCD_RM_L (0x1 << 9)
1800 #define RT5670_M_ZCD_RM_R (0x1 << 8)
1801 #define RT5670_M_ZCD_SM_L (0x1 << 7)
1802 #define RT5670_M_ZCD_SM_R (0x1 << 6)
1803 #define RT5670_M_ZCD_OM_L (0x1 << 5)
1804 #define RT5670_M_ZCD_OM_R (0x1 << 4)
1809 #define RT5670_ZCD_HP_MASK (0x1 << 15)
1812 #define RT5670_ZCD_HP_EN (0x1 << 15)
1815 #define RT5670_TDM_DATA_MODE_SEL (0x1 << 11)
1817 #define RT5670_TDM_DATA_MODE_50FS (0x1 << 11)
1821 #define RT5670_3D_SPK_MASK (0x1 << 15)
1824 #define RT5670_3D_SPK_EN (0x1 << 15)
1833 #define RT5670_WND_MASK (0x1 << 15)
1836 #define RT5670_WND_EN (0x1 << 15)
1859 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1861 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1872 #define RT5670_DP_SPK_MASK (0x1 << 10)
1875 #define RT5670_DP_SPK_EN (0x1 << 10)
1887 #define RT5670_JD_CBJ_EN (0x1 << 7)
1888 #define RT5670_JD_CBJ_POL (0x1 << 6)
1892 #define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
1901 #define RT5670_JD_HPO_JD1_1 (0x1)
1909 #define RT5670_RST_DSP (0x1 << 13)
1910 #define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1912 #define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1914 #define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1916 #define RT5670_MCLK_DET (0x1 << 3)
1919 #define RT5670_RXDC_SRC_MASK (0x1 << 7)
1921 #define RT5670_RXDC_SRC_MONO (0x1 << 7)
1923 #define RT5670_RXDP2_SEL_MASK (0x1 << 3)
1925 #define RT5670_RXDP2_SEL_ADC (0x1 << 3)
1974 RT5670_DA_STEREO_FILTER = 0x1,
1975 RT5670_DA_MONO_L_FILTER = (0x1 << 1),
1976 RT5670_DA_MONO_R_FILTER = (0x1 << 2),
1977 RT5670_AD_STEREO_FILTER = (0x1 << 3),
1978 RT5670_AD_MONO_L_FILTER = (0x1 << 4),
1979 RT5670_AD_MONO_R_FILTER = (0x1 << 5),
1980 RT5670_UP_RATE_FILTER = (0x1 << 6),
1981 RT5670_DOWN_RATE_FILTER = (0x1 << 7),