Lines Matching refs:x1
182 #define RT5640_L_MUTE (0x1 << 15)
184 #define RT5640_VOL_L_MUTE (0x1 << 14)
186 #define RT5640_R_MUTE (0x1 << 7)
188 #define RT5640_VOL_R_MUTE (0x1 << 6)
206 #define RT5640_IN_DF1 (0x1 << 7)
208 #define RT5640_IN_DF2 (0x1 << 6)
212 #define RT5640_INL_SEL_MASK (0x1 << 15)
215 #define RT5640_INL_SEL_MONOP (0x1 << 15)
218 #define RT5640_INR_SEL_MASK (0x1 << 7)
221 #define RT5640_INR_SEL_MONON (0x1 << 7)
238 #define RT5640_M_DAC_L2_VOL (0x1 << 13)
240 #define RT5640_M_DAC_R2_VOL (0x1 << 12)
264 #define RT5640_M_ADC_L1 (0x1 << 14)
266 #define RT5640_M_ADC_L2 (0x1 << 13)
268 #define RT5640_ADC_1_SRC_MASK (0x1 << 12)
270 #define RT5640_ADC_1_SRC_ADC (0x1 << 12)
275 #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
277 #define RT5640_M_ADC_R1 (0x1 << 6)
279 #define RT5640_M_ADC_R2 (0x1 << 5)
283 #define RT5640_M_MONO_ADC_L1 (0x1 << 14)
285 #define RT5640_M_MONO_ADC_L2 (0x1 << 13)
287 #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
290 #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
294 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
296 #define RT5640_M_MONO_ADC_R1 (0x1 << 6)
298 #define RT5640_M_MONO_ADC_R2 (0x1 << 5)
300 #define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
302 #define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
307 #define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
311 #define RT5640_M_ADCMIX_L (0x1 << 15)
313 #define RT5640_M_IF1_DAC_L (0x1 << 14)
315 #define RT5640_M_ADCMIX_R (0x1 << 7)
317 #define RT5640_M_IF1_DAC_R (0x1 << 6)
321 #define RT5640_M_DAC_L1 (0x1 << 14)
323 #define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
325 #define RT5640_M_DAC_L2 (0x1 << 12)
327 #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
329 #define RT5640_M_ANC_DAC_L (0x1 << 10)
331 #define RT5640_M_DAC_R1 (0x1 << 6)
333 #define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
335 #define RT5640_M_DAC_R2 (0x1 << 4)
337 #define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
339 #define RT5640_M_ANC_DAC_R (0x1 << 2)
343 #define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
345 #define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
347 #define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
349 #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
351 #define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
353 #define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
355 #define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
357 #define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
359 #define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
361 #define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
363 #define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
365 #define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
369 #define RT5640_M_STO_L_DAC_L (0x1 << 15)
371 #define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
373 #define RT5640_M_DAC_L2_DAC_L (0x1 << 13)
375 #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
377 #define RT5640_M_STO_R_DAC_R (0x1 << 11)
379 #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
381 #define RT5640_M_DAC_R2_DAC_R (0x1 << 9)
383 #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
387 #define RT5640_RXDP_SRC_MASK (0x1 << 15)
390 #define RT5640_RXDP_SRC_DIV3 (0x1 << 15)
391 #define RT5640_TXDP_SRC_MASK (0x1 << 14)
394 #define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
400 #define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
406 #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
408 #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
411 #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
412 #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
415 #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
419 #define RT5640_RXDC_SEL_L2R (0x1 << 8)
425 #define RT5640_RXDP_SEL_L2R (0x1 << 6)
431 #define RT5640_TXDC_SEL_L2R (0x1 << 4)
437 #define RT5640_TXDP_SEL_L2R (0x1 << 2)
445 #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
451 #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
457 #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
463 #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
469 #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
475 #define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
496 #define RT5640_M_HP_L_RM_L (0x1 << 6)
498 #define RT5640_M_IN_L_RM_L (0x1 << 5)
500 #define RT5640_M_BST4_RM_L (0x1 << 4)
502 #define RT5640_M_BST3_RM_L (0x1 << 3)
504 #define RT5640_M_BST2_RM_L (0x1 << 2)
506 #define RT5640_M_BST1_RM_L (0x1 << 1)
508 #define RT5640_M_OM_L_RM_L (0x1)
528 #define RT5640_M_HP_R_RM_R (0x1 << 6)
530 #define RT5640_M_IN_R_RM_R (0x1 << 5)
532 #define RT5640_M_BST4_RM_R (0x1 << 4)
534 #define RT5640_M_BST3_RM_R (0x1 << 3)
536 #define RT5640_M_BST2_RM_R (0x1 << 2)
538 #define RT5640_M_BST1_RM_R (0x1 << 1)
540 #define RT5640_M_OM_R_RM_R (0x1)
544 #define RT5640_M_DAC2_HM (0x1 << 15)
546 #define RT5640_M_DAC1_HM (0x1 << 14)
548 #define RT5640_M_HPVOL_HM (0x1 << 13)
550 #define RT5640_G_HPOMIX_MASK (0x1 << 12)
564 #define RT5640_M_RM_L_SM_L (0x1 << 5)
566 #define RT5640_M_IN_L_SM_L (0x1 << 4)
568 #define RT5640_M_DAC_L1_SM_L (0x1 << 3)
570 #define RT5640_M_DAC_L2_SM_L (0x1 << 2)
572 #define RT5640_M_OM_L_SM_L (0x1 << 1)
586 #define RT5640_M_RM_R_SM_R (0x1 << 5)
588 #define RT5640_M_IN_R_SM_R (0x1 << 4)
590 #define RT5640_M_DAC_R1_SM_R (0x1 << 3)
592 #define RT5640_M_DAC_R2_SM_R (0x1 << 2)
594 #define RT5640_M_OM_R_SM_R (0x1 << 1)
598 #define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
600 #define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
602 #define RT5640_M_SV_R_SPM_L (0x1 << 13)
604 #define RT5640_M_SV_L_SPM_L (0x1 << 12)
606 #define RT5640_M_BST1_SPM_L (0x1 << 11)
610 #define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
612 #define RT5640_M_SV_R_SPM_R (0x1 << 12)
614 #define RT5640_M_BST1_SPM_R (0x1 << 11)
622 #define RT5640_M_DAC_R2_MM (0x1 << 15)
624 #define RT5640_M_DAC_L2_MM (0x1 << 14)
626 #define RT5640_M_OV_R_MM (0x1 << 13)
628 #define RT5640_M_OV_L_MM (0x1 << 12)
630 #define RT5640_M_BST1_MM (0x1 << 11)
632 #define RT5640_G_MONOMIX_MASK (0x1 << 10)
656 #define RT5640_M_SM_L_OM_L (0x1 << 8)
658 #define RT5640_M_BST3_OM_L (0x1 << 7)
660 #define RT5640_M_BST2_OM_L (0x1 << 6)
662 #define RT5640_M_BST1_OM_L (0x1 << 5)
664 #define RT5640_M_IN_L_OM_L (0x1 << 4)
666 #define RT5640_M_RM_L_OM_L (0x1 << 3)
668 #define RT5640_M_DAC_R2_OM_L (0x1 << 2)
670 #define RT5640_M_DAC_L2_OM_L (0x1 << 1)
672 #define RT5640_M_DAC_L1_OM_L (0x1)
696 #define RT5640_M_SM_L_OM_R (0x1 << 8)
698 #define RT5640_M_BST4_OM_R (0x1 << 7)
700 #define RT5640_M_BST2_OM_R (0x1 << 6)
702 #define RT5640_M_BST1_OM_R (0x1 << 5)
704 #define RT5640_M_IN_R_OM_R (0x1 << 4)
706 #define RT5640_M_RM_R_OM_R (0x1 << 3)
708 #define RT5640_M_DAC_L2_OM_R (0x1 << 2)
710 #define RT5640_M_DAC_R2_OM_R (0x1 << 1)
712 #define RT5640_M_DAC_R1_OM_R (0x1)
716 #define RT5640_M_DAC_L1_LM (0x1 << 15)
718 #define RT5640_M_DAC_R1_LM (0x1 << 14)
720 #define RT5640_M_OV_L_LM (0x1 << 13)
722 #define RT5640_M_OV_R_LM (0x1 << 12)
724 #define RT5640_G_LOUTMIX_MASK (0x1 << 11)
728 #define RT5640_PWR_I2S1 (0x1 << 15)
730 #define RT5640_PWR_I2S2 (0x1 << 14)
732 #define RT5640_PWR_DAC_L1 (0x1 << 12)
734 #define RT5640_PWR_DAC_R1 (0x1 << 11)
736 #define RT5640_PWR_DAC_L2 (0x1 << 7)
738 #define RT5640_PWR_DAC_R2 (0x1 << 6)
740 #define RT5640_PWR_ADC_L (0x1 << 2)
742 #define RT5640_PWR_ADC_R (0x1 << 1)
744 #define RT5640_PWR_CLS_D (0x1)
748 #define RT5640_PWR_ADC_SF (0x1 << 15)
750 #define RT5640_PWR_ADC_MF_L (0x1 << 14)
752 #define RT5640_PWR_ADC_MF_R (0x1 << 13)
754 #define RT5640_PWR_I2S_DSP (0x1 << 12)
758 #define RT5640_PWR_VREF1 (0x1 << 15)
760 #define RT5640_PWR_FV1 (0x1 << 14)
762 #define RT5640_PWR_MB (0x1 << 13)
764 #define RT5640_PWR_LM (0x1 << 12)
766 #define RT5640_PWR_BG (0x1 << 11)
768 #define RT5640_PWR_MM (0x1 << 10)
770 #define RT5640_PWR_MA (0x1 << 8)
772 #define RT5640_PWR_HP_L (0x1 << 7)
774 #define RT5640_PWR_HP_R (0x1 << 6)
776 #define RT5640_PWR_HA (0x1 << 5)
778 #define RT5640_PWR_VREF2 (0x1 << 4)
780 #define RT5640_PWR_FV2 (0x1 << 3)
782 #define RT5640_PWR_LDO2 (0x1 << 2)
786 #define RT5640_PWR_BST1 (0x1 << 15)
788 #define RT5640_PWR_BST2 (0x1 << 14)
790 #define RT5640_PWR_BST3 (0x1 << 13)
792 #define RT5640_PWR_BST4 (0x1 << 12)
794 #define RT5640_PWR_MB1 (0x1 << 11)
796 #define RT5640_PWR_PLL (0x1 << 9)
800 #define RT5640_PWR_OM_L (0x1 << 15)
802 #define RT5640_PWR_OM_R (0x1 << 14)
804 #define RT5640_PWR_SM_L (0x1 << 13)
806 #define RT5640_PWR_SM_R (0x1 << 12)
808 #define RT5640_PWR_RM_L (0x1 << 11)
810 #define RT5640_PWR_RM_R (0x1 << 10)
814 #define RT5640_PWR_SV_L (0x1 << 15)
816 #define RT5640_PWR_SV_R (0x1 << 14)
818 #define RT5640_PWR_OV_L (0x1 << 13)
820 #define RT5640_PWR_OV_R (0x1 << 12)
822 #define RT5640_PWR_HV_L (0x1 << 11)
824 #define RT5640_PWR_HV_R (0x1 << 10)
826 #define RT5640_PWR_IN_L (0x1 << 9)
828 #define RT5640_PWR_IN_R (0x1 << 8)
832 #define RT5640_I2S_MS_MASK (0x1 << 15)
835 #define RT5640_I2S_MS_S (0x1 << 15)
841 #define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
846 #define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
848 #define RT5640_I2S_BP_MASK (0x1 << 7)
851 #define RT5640_I2S_BP_INV (0x1 << 7)
855 #define RT5640_I2S_DL_20 (0x1 << 2)
861 #define RT5640_I2S_DF_LEFT (0x1)
866 #define RT5640_I2S2_SDI_MASK (0x1 << 6)
869 #define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
872 #define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
875 #define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
879 #define RT5640_I2S_PD1_2 (0x1 << 12)
886 #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
889 #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
893 #define RT5640_I2S_PD2_2 (0x1 << 8)
900 #define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7)
903 #define RT5640_I2S_BCLK_MS3_64 (0x1 << 7)
907 #define RT5640_I2S_PD3_2 (0x1 << 4)
917 #define RT5640_DAC_OSR_64 (0x1 << 2)
923 #define RT5640_ADC_OSR_64 (0x1)
931 #define RT5640_DAC_L_OSR_64 (0x1 << 14)
937 #define RT5640_ADC_R_OSR_64 (0x1 << 12)
940 #define RT5640_DAHPF_EN (0x1 << 11)
942 #define RT5640_ADHPF_EN (0x1 << 10)
946 #define RT5640_DMIC_1_EN_MASK (0x1 << 15)
949 #define RT5640_DMIC_1_EN (0x1 << 15)
950 #define RT5640_DMIC_2_EN_MASK (0x1 << 14)
953 #define RT5640_DMIC_2_EN (0x1 << 14)
954 #define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
957 #define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
958 #define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
961 #define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
962 #define RT5640_DMIC_1_DP_MASK (0x1 << 11)
965 #define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
966 #define RT5640_DMIC_2_DP_MASK (0x1 << 10)
969 #define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
970 #define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
973 #define RT5640_DMIC_2L_LH_RISING (0x1 << 9)
974 #define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
977 #define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
985 #define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
990 #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
993 #define RT5640_PLL1_PD_MASK (0x1 << 3)
996 #define RT5640_PLL1_PD_2 (0x1 << 3)
1012 #define RT5640_PLL_M_BP (0x1 << 11)
1016 #define RT5640_STO_T_MASK (0x1 << 15)
1019 #define RT5640_STO_T_LRCK1 (0x1 << 15)
1020 #define RT5640_M1_T_MASK (0x1 << 14)
1023 #define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1024 #define RT5640_I2S2_F_MASK (0x1 << 12)
1027 #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1028 #define RT5640_DMIC_1_M_MASK (0x1 << 9)
1031 #define RT5640_DMIC_1_M_ASYN (0x1 << 9)
1032 #define RT5640_DMIC_2_M_MASK (0x1 << 8)
1035 #define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1039 #define RT5640_CLK_SEL_ASRC (0x1)
1042 #define RT5640_MDA_L_M_MASK (0x1 << 15)
1045 #define RT5640_MDA_L_M_ASYN (0x1 << 15)
1046 #define RT5640_MDA_R_M_MASK (0x1 << 14)
1049 #define RT5640_MDA_R_M_ASYN (0x1 << 14)
1050 #define RT5640_MAD_L_M_MASK (0x1 << 13)
1053 #define RT5640_MAD_L_M_ASYN (0x1 << 13)
1054 #define RT5640_MAD_R_M_MASK (0x1 << 12)
1057 #define RT5640_MAD_R_M_ASYN (0x1 << 12)
1058 #define RT5640_ADC_M_MASK (0x1 << 11)
1061 #define RT5640_ADC_M_ASYN (0x1 << 11)
1062 #define RT5640_STO_DAC_M_MASK (0x1 << 5)
1065 #define RT5640_STO_DAC_M_ASYN (0x1 << 5)
1066 #define RT5640_I2S1_R_D_MASK (0x1 << 4)
1069 #define RT5640_I2S1_R_D_EN (0x1 << 4)
1070 #define RT5640_I2S2_R_D_MASK (0x1 << 3)
1073 #define RT5640_I2S2_R_D_EN (0x1 << 3)
1077 #define RT5640_PRE_SCLK_1024 (0x1)
1093 #define RT5640_HP_OVCD_MASK (0x1 << 10)
1096 #define RT5640_HP_OVCD_EN (0x1 << 10)
1100 #define RT5640_HP_OC_TH_105 (0x1 << 8)
1105 #define RT5640_CLSD_OC_MASK (0x1 << 9)
1108 #define RT5640_CLSD_OC_PD (0x1 << 9)
1109 #define RT5640_AUTO_PD_MASK (0x1 << 8)
1112 #define RT5640_AUTO_PD_EN (0x1 << 8)
1119 #define RT5640_CLSD_OM_MASK (0x1 << 11)
1122 #define RT5640_CLSD_OM_STO (0x1 << 11)
1123 #define RT5640_CLSD_SCH_MASK (0x1 << 10)
1126 #define RT5640_CLSD_SCH_S (0x1 << 10)
1129 #define RT5640_SMT_TRIG_MASK (0x1 << 15)
1132 #define RT5640_SMT_TRIG_EN (0x1 << 15)
1133 #define RT5640_HP_L_SMT_MASK (0x1 << 9)
1136 #define RT5640_HP_L_SMT_EN (0x1 << 9)
1137 #define RT5640_HP_R_SMT_MASK (0x1 << 8)
1140 #define RT5640_HP_R_SMT_EN (0x1 << 8)
1141 #define RT5640_HP_CD_PD_MASK (0x1 << 7)
1144 #define RT5640_HP_CD_PD_EN (0x1 << 7)
1145 #define RT5640_RSTN_MASK (0x1 << 6)
1148 #define RT5640_RSTN_EN (0x1 << 6)
1149 #define RT5640_RSTP_MASK (0x1 << 5)
1152 #define RT5640_RSTP_EN (0x1 << 5)
1153 #define RT5640_HP_CO_MASK (0x1 << 4)
1156 #define RT5640_HP_CO_EN (0x1 << 4)
1157 #define RT5640_HP_CP_MASK (0x1 << 3)
1160 #define RT5640_HP_CP_PU (0x1 << 3)
1161 #define RT5640_HP_SG_MASK (0x1 << 2)
1164 #define RT5640_HP_SG_EN (0x1 << 2)
1165 #define RT5640_HP_DP_MASK (0x1 << 1)
1168 #define RT5640_HP_DP_PU (0x1 << 1)
1169 #define RT5640_HP_CB_MASK (0x1)
1172 #define RT5640_HP_CB_PU (0x1)
1175 #define RT5640_DEPOP_MASK (0x1 << 13)
1178 #define RT5640_DEPOP_MAN (0x1 << 13)
1179 #define RT5640_RAMP_MASK (0x1 << 12)
1182 #define RT5640_RAMP_EN (0x1 << 12)
1183 #define RT5640_BPS_MASK (0x1 << 11)
1186 #define RT5640_BPS_EN (0x1 << 11)
1187 #define RT5640_FAST_UPDN_MASK (0x1 << 10)
1190 #define RT5640_FAST_UPDN_EN (0x1 << 10)
1194 #define RT5640_MRES_25MO (0x1 << 8)
1197 #define RT5640_VLO_MASK (0x1 << 7)
1200 #define RT5640_VLO_32V (0x1 << 7)
1201 #define RT5640_DIG_DP_MASK (0x1 << 6)
1204 #define RT5640_DIG_DP_EN (0x1 << 6)
1227 #define RT5640_OSW_L_MASK (0x1 << 11)
1230 #define RT5640_OSW_L_EN (0x1 << 11)
1231 #define RT5640_OSW_R_MASK (0x1 << 10)
1234 #define RT5640_OSW_R_EN (0x1 << 10)
1238 #define RT5640_PM_HP_MV (0x1 << 8)
1243 #define RT5640_IB_HP_25IL (0x1 << 6)
1248 #define RT5640_PVDD_DET_MASK (0x1 << 15)
1251 #define RT5640_PVDD_DET_EN (0x1 << 15)
1252 #define RT5640_SPK_AG_MASK (0x1 << 14)
1255 #define RT5640_SPK_AG_EN (0x1 << 14)
1258 #define RT5640_MIC1_BS_MASK (0x1 << 15)
1261 #define RT5640_MIC1_BS_75AV (0x1 << 15)
1262 #define RT5640_MIC2_BS_MASK (0x1 << 14)
1265 #define RT5640_MIC2_BS_75AV (0x1 << 14)
1266 #define RT5640_MIC1_CLK_MASK (0x1 << 13)
1269 #define RT5640_MIC1_CLK_EN (0x1 << 13)
1270 #define RT5640_MIC2_CLK_MASK (0x1 << 12)
1273 #define RT5640_MIC2_CLK_EN (0x1 << 12)
1274 #define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1277 #define RT5640_MIC1_OVCD_EN (0x1 << 11)
1281 #define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
1283 #define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1286 #define RT5640_MIC2_OVCD_EN (0x1 << 8)
1290 #define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1292 #define RT5640_PWR_MB_MASK (0x1 << 5)
1295 #define RT5640_PWR_MB_PU (0x1 << 5)
1296 #define RT5640_PWR_CLK25M_MASK (0x1 << 4)
1299 #define RT5640_PWR_CLK25M_PU (0x1 << 4)
1302 #define RT5640_EQ_SRC_MASK (0x1 << 15)
1305 #define RT5640_EQ_SRC_ADC (0x1 << 15)
1306 #define RT5640_EQ_UPD (0x1 << 14)
1308 #define RT5640_EQ_CD_MASK (0x1 << 13)
1311 #define RT5640_EQ_CD_EN (0x1 << 13)
1315 #define RT5640_EQ_DITH_LSB (0x1 << 8)
1320 #define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1323 #define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1324 #define RT5640_EQ_LPF1_M_MASK (0x1 << 7)
1327 #define RT5640_EQ_LPF1_M_1ST (0x1 << 7)
1328 #define RT5640_EQ_HPF2_MASK (0x1 << 6)
1331 #define RT5640_EQ_HPF2_EN (0x1 << 6)
1332 #define RT5640_EQ_HPF1_MASK (0x1 << 5)
1335 #define RT5640_EQ_HPF1_EN (0x1 << 5)
1336 #define RT5640_EQ_BPF4_MASK (0x1 << 4)
1339 #define RT5640_EQ_BPF4_EN (0x1 << 4)
1340 #define RT5640_EQ_BPF3_MASK (0x1 << 3)
1343 #define RT5640_EQ_BPF3_EN (0x1 << 3)
1344 #define RT5640_EQ_BPF2_MASK (0x1 << 2)
1347 #define RT5640_EQ_BPF2_EN (0x1 << 2)
1348 #define RT5640_EQ_BPF1_MASK (0x1 << 1)
1351 #define RT5640_EQ_BPF1_EN (0x1 << 1)
1352 #define RT5640_EQ_LPF_MASK (0x1)
1355 #define RT5640_EQ_LPF_EN (0x1)
1358 #define RT5640_MT_MASK (0x1 << 15)
1361 #define RT5640_MT_EN (0x1 << 15)
1364 #define RT5640_DRC_AGC_P_MASK (0x1 << 15)
1367 #define RT5640_DRC_AGC_P_ADC (0x1 << 15)
1368 #define RT5640_DRC_AGC_MASK (0x1 << 14)
1371 #define RT5640_DRC_AGC_EN (0x1 << 14)
1372 #define RT5640_DRC_AGC_UPD (0x1 << 13)
1378 #define RT5640_DRC_AGC_R_48K (0x1 << 5)
1390 #define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
1393 #define RT5640_DRC_AGC_CP_EN (0x1 << 7)
1397 #define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
1408 #define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1411 #define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1412 #define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
1415 #define RT5640_DRC_AGC_NGH_EN (0x1 << 5)
1420 #define RT5640_ANC_M_MASK (0x1 << 15)
1423 #define RT5640_ANC_M_REV (0x1 << 15)
1424 #define RT5640_ANC_MASK (0x1 << 14)
1427 #define RT5640_ANC_EN (0x1 << 14)
1431 #define RT5640_ANC_MD_67MS (0x1 << 12)
1434 #define RT5640_ANC_SN_MASK (0x1 << 11)
1437 #define RT5640_ANC_SN_EN (0x1 << 11)
1438 #define RT5640_ANC_CLK_MASK (0x1 << 10)
1441 #define RT5640_ANC_CLK_REG (0x1 << 10)
1445 #define RT5640_ANC_ZCD_T1 (0x1 << 8)
1448 #define RT5640_ANC_CS_MASK (0x1 << 7)
1451 #define RT5640_ANC_CS_EN (0x1 << 7)
1452 #define RT5640_ANC_SW_MASK (0x1 << 6)
1455 #define RT5640_ANC_SW_AUTO (0x1 << 6)
1470 #define RT5640_ANC_CD_MASK (0x1 << 6)
1473 #define RT5640_ANC_CD_IND (0x1 << 6)
1481 #define RT5640_JD_GPIO1 (0x1 << 13)
1487 #define RT5640_JD_HP_MASK (0x1 << 11)
1490 #define RT5640_JD_HP_EN (0x1 << 11)
1491 #define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1494 #define RT5640_JD_HP_TRG_HI (0x1 << 10)
1495 #define RT5640_JD_SPL_MASK (0x1 << 9)
1498 #define RT5640_JD_SPL_EN (0x1 << 9)
1499 #define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1502 #define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1503 #define RT5640_JD_SPR_MASK (0x1 << 7)
1506 #define RT5640_JD_SPR_EN (0x1 << 7)
1507 #define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1510 #define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1511 #define RT5640_JD_MO_MASK (0x1 << 5)
1514 #define RT5640_JD_MO_EN (0x1 << 5)
1515 #define RT5640_JD_MO_TRG_MASK (0x1 << 4)
1518 #define RT5640_JD_MO_TRG_HI (0x1 << 4)
1519 #define RT5640_JD_LO_MASK (0x1 << 3)
1522 #define RT5640_JD_LO_EN (0x1 << 3)
1523 #define RT5640_JD_LO_TRG_MASK (0x1 << 2)
1526 #define RT5640_JD_LO_TRG_HI (0x1 << 2)
1527 #define RT5640_JD1_IN4P_MASK (0x1 << 1)
1530 #define RT5640_JD1_IN4P_EN (0x1 << 1)
1531 #define RT5640_JD2_IN4N_MASK (0x1)
1534 #define RT5640_JD2_IN4N_EN (0x1)
1540 #define RT5640_ANC_DET_MB1 (0x1 << 4)
1543 #define RT5640_AD_TRG_MASK (0x1 << 3)
1546 #define RT5640_AD_TRG_HI (0x1 << 3)
1550 #define RT5640_ANCM_DET_MB1 (0x1 << 4)
1553 #define RT5640_AMD_TRG_MASK (0x1 << 3)
1556 #define RT5640_AMD_TRG_HI (0x1 << 3)
1559 #define RT5640_IRQ_JD_MASK (0x1 << 15)
1562 #define RT5640_IRQ_JD_NOR (0x1 << 15)
1563 #define RT5640_IRQ_OT_MASK (0x1 << 14)
1566 #define RT5640_IRQ_OT_NOR (0x1 << 14)
1567 #define RT5640_JD_STKY_MASK (0x1 << 13)
1570 #define RT5640_JD_STKY_EN (0x1 << 13)
1571 #define RT5640_OT_STKY_MASK (0x1 << 12)
1574 #define RT5640_OT_STKY_EN (0x1 << 12)
1575 #define RT5640_JD_P_MASK (0x1 << 11)
1578 #define RT5640_JD_P_INV (0x1 << 11)
1579 #define RT5640_OT_P_MASK (0x1 << 10)
1582 #define RT5640_OT_P_INV (0x1 << 10)
1585 #define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
1588 #define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
1589 #define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1592 #define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1593 #define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1596 #define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1597 #define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1600 #define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1601 #define RT5640_MB1_OC_P_MASK (0x1 << 7)
1604 #define RT5640_MB1_OC_P_INV (0x1 << 7)
1605 #define RT5640_MB2_OC_P_MASK (0x1 << 6)
1608 #define RT5640_MB2_OC_P_INV (0x1 << 6)
1609 #define RT5640_MB1_OC_STATUS (0x1 << 3)
1611 #define RT5640_MB2_OC_STATUS (0x1 << 2)
1615 #define RT5640_GPIO1_STATUS (0x1 << 8)
1616 #define RT5640_GPIO2_STATUS (0x1 << 7)
1617 #define RT5640_JD_STATUS (0x1 << 4)
1618 #define RT5640_OVT_STATUS (0x1 << 3)
1619 #define RT5640_CLS_D_OVCD_STATUS (0x1 << 0)
1622 #define RT5640_GP1_PIN_MASK (0x1 << 15)
1625 #define RT5640_GP1_PIN_IRQ (0x1 << 15)
1626 #define RT5640_GP2_PIN_MASK (0x1 << 14)
1629 #define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1633 #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1635 #define RT5640_GP4_PIN_MASK (0x1 << 11)
1638 #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1639 #define RT5640_DP_SIG_MASK (0x1 << 10)
1642 #define RT5640_DP_SIG_AP (0x1 << 10)
1643 #define RT5640_GPIO_M_MASK (0x1 << 9)
1646 #define RT5640_GPIO_M_PH (0x1 << 9)
1649 #define RT5640_GP4_PF_MASK (0x1 << 11)
1652 #define RT5640_GP4_PF_OUT (0x1 << 11)
1653 #define RT5640_GP4_OUT_MASK (0x1 << 10)
1656 #define RT5640_GP4_OUT_HI (0x1 << 10)
1657 #define RT5640_GP4_P_MASK (0x1 << 9)
1660 #define RT5640_GP4_P_INV (0x1 << 9)
1661 #define RT5640_GP3_PF_MASK (0x1 << 8)
1664 #define RT5640_GP3_PF_OUT (0x1 << 8)
1665 #define RT5640_GP3_OUT_MASK (0x1 << 7)
1668 #define RT5640_GP3_OUT_HI (0x1 << 7)
1669 #define RT5640_GP3_P_MASK (0x1 << 6)
1672 #define RT5640_GP3_P_INV (0x1 << 6)
1673 #define RT5640_GP2_PF_MASK (0x1 << 5)
1676 #define RT5640_GP2_PF_OUT (0x1 << 5)
1677 #define RT5640_GP2_OUT_MASK (0x1 << 4)
1680 #define RT5640_GP2_OUT_HI (0x1 << 4)
1681 #define RT5640_GP2_P_MASK (0x1 << 3)
1684 #define RT5640_GP2_P_INV (0x1 << 3)
1685 #define RT5640_GP1_PF_MASK (0x1 << 2)
1688 #define RT5640_GP1_PF_OUT (0x1 << 2)
1689 #define RT5640_GP1_OUT_MASK (0x1 << 1)
1692 #define RT5640_GP1_OUT_HI (0x1 << 1)
1693 #define RT5640_GP1_P_MASK (0x1)
1696 #define RT5640_GP1_P_INV (0x1)
1705 #define RT5640_DSP_BUSY_MASK (0x1 << 15)
1707 #define RT5640_DSP_DS_MASK (0x1 << 14)
1709 #define RT5640_DSP_DS_FM3010 (0x1 << 14)
1710 #define RT5640_DSP_DS_TEMP (0x1 << 14)
1714 #define RT5640_DSP_CLK_192K (0x1 << 12)
1717 #define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1720 #define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1721 #define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1724 #define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1725 #define RT5640_DSP_R_EN (0x1 << 9)
1727 #define RT5640_DSP_W_EN (0x1 << 8)
1739 #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1742 #define RT5640_SEQ1_ST_FIN (0x1 << 11)
1743 #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1746 #define RT5640_SEQ2_ST_FIN (0x1 << 10)
1747 #define RT5640_REG_LV_MASK (0x1 << 9)
1750 #define RT5640_REG_LV_PR (0x1 << 9)
1751 #define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1763 #define RT5640_PROG_MASK (0x1 << 7)
1766 #define RT5640_PROG_EN (0x1 << 7)
1767 #define RT5640_SEQ1_PT_RUN (0x1 << 6)
1769 #define RT5640_SEQ2_PT_RUN (0x1 << 5)
1789 #define RT5640_SCB_SWAP_MASK (0x1 << 15)
1792 #define RT5640_SCB_SWAP_EN (0x1 << 15)
1793 #define RT5640_SCB_MASK (0x1 << 14)
1796 #define RT5640_SCB_EN (0x1 << 14)
1799 #define RT5640_BB_MASK (0x1 << 15)
1802 #define RT5640_BB_EN (0x1 << 15)
1806 #define RT5640_BB_CT_B (0x1 << 12)
1809 #define RT5640_M_BB_L_MASK (0x1 << 9)
1811 #define RT5640_M_BB_R_MASK (0x1 << 8)
1813 #define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
1815 #define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1821 #define RT5640_M_MP3_L_MASK (0x1 << 15)
1823 #define RT5640_M_MP3_R_MASK (0x1 << 14)
1825 #define RT5640_M_MP3_MASK (0x1 << 13)
1828 #define RT5640_M_MP3_EN (0x1 << 13)
1831 #define RT5640_MP3_HLP_MASK (0x1 << 7)
1834 #define RT5640_MP3_HLP_EN (0x1 << 7)
1835 #define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1837 #define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
1841 #define RT5640_MP3_WT_MASK (0x1 << 13)
1844 #define RT5640_MP3_WT_1_2 (0x1 << 13)
1851 #define RT5640_3D_CF_MASK (0x1 << 15)
1854 #define RT5640_3D_CF_EN (0x1 << 15)
1855 #define RT5640_3D_HP_MASK (0x1 << 14)
1858 #define RT5640_3D_HP_EN (0x1 << 14)
1859 #define RT5640_3D_BT_MASK (0x1 << 13)
1862 #define RT5640_3D_BT_EN (0x1 << 13)
1865 #define RT5640_3D_HP_M_MASK (0x1 << 10)
1868 #define RT5640_3D_HP_M_FRO (0x1 << 10)
1869 #define RT5640_M_3D_HRTF_MASK (0x1 << 9)
1871 #define RT5640_M_3D_D2H_MASK (0x1 << 8)
1873 #define RT5640_M_3D_D2R_MASK (0x1 << 7)
1875 #define RT5640_M_3D_REVB_MASK (0x1 << 6)
1879 #define RT5640_2ND_HPF_MASK (0x1 << 15)
1882 #define RT5640_2ND_HPF_EN (0x1 << 15)
1885 #define RT5640_1ST_HPF_MASK (0x1 << 11)
1888 #define RT5640_1ST_HPF_EN (0x1 << 11)
1896 #define RT5640_ZD_F_ZC_IM (0x1 << 4)
1901 #define RT5640_SI_DAC_MASK (0x1 << 11)
1904 #define RT5640_SI_DAC_TEST (0x1 << 11)
1905 #define RT5640_DC_CAL_M_MASK (0x1 << 10)
1908 #define RT5640_DC_CAL_M_NOR (0x1 << 10)
1909 #define RT5640_DC_CAL_MASK (0x1 << 9)
1912 #define RT5640_DC_CAL_EN (0x1 << 9)
1915 #define RT5640_HPD_PS_MASK (0x1 << 5)
1918 #define RT5640_HPD_PS_EN (0x1 << 5)
1919 #define RT5640_CAL_M_MASK (0x1 << 4)
1922 #define RT5640_CAL_M_CAL (0x1 << 4)
1923 #define RT5640_CAL_MASK (0x1 << 3)
1926 #define RT5640_CAL_EN (0x1 << 3)
1927 #define RT5640_CAL_TEST_MASK (0x1 << 2)
1930 #define RT5640_CAL_TEST_EN (0x1 << 2)
1934 #define RT5640_CAL_P_CAL (0x1)
1938 #define RT5640_SV_MASK (0x1 << 15)
1941 #define RT5640_SV_EN (0x1 << 15)
1942 #define RT5640_SPO_SV_MASK (0x1 << 14)
1945 #define RT5640_SPO_SV_EN (0x1 << 14)
1946 #define RT5640_OUT_SV_MASK (0x1 << 13)
1949 #define RT5640_OUT_SV_EN (0x1 << 13)
1950 #define RT5640_HP_SV_MASK (0x1 << 12)
1953 #define RT5640_HP_SV_EN (0x1 << 12)
1954 #define RT5640_ZCD_DIG_MASK (0x1 << 11)
1957 #define RT5640_ZCD_DIG_EN (0x1 << 11)
1958 #define RT5640_ZCD_MASK (0x1 << 10)
1961 #define RT5640_ZCD_PU (0x1 << 10)
1964 #define RT5640_M_ZCD_RM_L (0x1 << 9)
1965 #define RT5640_M_ZCD_RM_R (0x1 << 8)
1966 #define RT5640_M_ZCD_SM_L (0x1 << 7)
1967 #define RT5640_M_ZCD_SM_R (0x1 << 6)
1968 #define RT5640_M_ZCD_OM_L (0x1 << 5)
1969 #define RT5640_M_ZCD_OM_R (0x1 << 4)
1974 #define RT5640_ZCD_HP_MASK (0x1 << 15)
1977 #define RT5640_ZCD_HP_EN (0x1 << 15)
1980 #define RT5640_M_MONO_ADC_L (0x1 << 13)
1982 #define RT5640_M_MONO_ADC_R (0x1 << 12)
1984 #define RT5640_MCLK_DET (0x1 << 11)
1992 #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8)
1997 #define RT5640_3D_SPK_MASK (0x1 << 15)
2000 #define RT5640_3D_SPK_EN (0x1 << 15)
2009 #define RT5640_WND_MASK (0x1 << 15)
2012 #define RT5640_WND_EN (0x1 << 15)
2035 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2037 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2048 #define RT5640_DP_SPK_MASK (0x1 << 10)
2051 #define RT5640_DP_SPK_EN (0x1 << 10)
2086 RT5640_U_IF1 = 0x1,
2111 RT5640_DA_STEREO_FILTER = 0x1,
2112 RT5640_DA_MONO_L_FILTER = (0x1 << 1),
2113 RT5640_DA_MONO_R_FILTER = (0x1 << 2),
2114 RT5640_AD_STEREO_FILTER = (0x1 << 3),
2115 RT5640_AD_MONO_L_FILTER = (0x1 << 4),
2116 RT5640_AD_MONO_R_FILTER = (0x1 << 5),