Lines Matching refs:x1
219 #define RT5645_L_MUTE (0x1 << 15)
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
223 #define RT5645_R_MUTE (0x1 << 7)
225 #define RT5645_VOL_R_MUTE (0x1 << 6)
235 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
238 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
239 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
240 #define RT5645_CBJ_MIC_SW (0x1 << 4)
241 #define RT5645_CBJ_BST1_EN (0x1 << 2)
244 #define RT5645_CBJ_MN_JD (0x1 << 12)
245 #define RT5645_CAPLESS_EN (0x1 << 11)
246 #define RT5645_CBJ_DET_MODE (0x1 << 7)
249 #define RT5645_CBJ_TIE_G_L (0x1 << 15)
250 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
257 #define RT5645_IN_DF2 (0x1 << 6)
261 #define RT5645_INL_SEL_MASK (0x1 << 15)
264 #define RT5645_INL_SEL_MONOP (0x1 << 15)
267 #define RT5645_INR_SEL_MASK (0x1 << 7)
270 #define RT5645_INR_SEL_MONON (0x1 << 7)
287 #define RT5645_M_DAC_L2_VOL (0x1 << 13)
289 #define RT5645_M_DAC_R2_VOL (0x1 << 12)
325 #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
329 #define RT5645_M_ADC_L1 (0x1 << 14)
331 #define RT5645_M_ADC_L2 (0x1 << 13)
333 #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
335 #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
337 #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
339 #define RT5645_DMIC_SRC_MASK (0x1 << 8)
341 #define RT5645_M_ADC_R1 (0x1 << 6)
343 #define RT5645_M_ADC_R2 (0x1 << 5)
345 #define RT5645_DMIC3_SRC_MASK (0x1 << 1)
349 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
351 #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
353 #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
356 #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
357 #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
359 #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
361 #define RT5645_M_MONO_ADC_R1 (0x1 << 6)
363 #define RT5645_M_MONO_ADC_R2 (0x1 << 5)
365 #define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
367 #define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
369 #define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
375 #define RT5645_M_ADCMIX_L (0x1 << 15)
377 #define RT5645_M_DAC1_L (0x1 << 14)
382 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
388 #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
391 #define RT5645_M_ADCMIX_R (0x1 << 7)
393 #define RT5645_M_DAC1_R (0x1 << 6)
397 #define RT5645_M_DAC_L1 (0x1 << 14)
399 #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
401 #define RT5645_M_DAC_L2 (0x1 << 12)
403 #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
405 #define RT5645_M_ANC_DAC_L (0x1 << 10)
407 #define RT5645_M_DAC_R1_STO_L (0x1 << 9)
409 #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
411 #define RT5645_M_DAC_R1 (0x1 << 6)
413 #define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
415 #define RT5645_M_DAC_R2 (0x1 << 4)
417 #define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
419 #define RT5645_M_ANC_DAC_R (0x1 << 2)
421 #define RT5645_M_DAC_L1_STO_R (0x1 << 1)
423 #define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
427 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
429 #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
431 #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
433 #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
435 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
437 #define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
439 #define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
441 #define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
443 #define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
445 #define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
447 #define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
449 #define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
453 #define RT5645_M_STO_L_DAC_L (0x1 << 15)
455 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
457 #define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
459 #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
461 #define RT5645_M_STO_R_DAC_R (0x1 << 11)
463 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
465 #define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
467 #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
469 #define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
471 #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
473 #define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
475 #define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
485 #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
501 #define RT5645_PDM1_L_MASK (0x1 << 15)
503 #define RT5645_M_PDM1_L (0x1 << 14)
505 #define RT5645_PDM1_R_MASK (0x1 << 13)
507 #define RT5645_M_PDM1_R (0x1 << 12)
509 #define RT5645_PDM2_L_MASK (0x1 << 11)
511 #define RT5645_M_PDM2_L (0x1 << 10)
513 #define RT5645_PDM2_R_MASK (0x1 << 9)
515 #define RT5645_M_PDM2_R (0x1 << 8)
517 #define RT5645_PDM2_BUSY (0x1 << 7)
518 #define RT5645_PDM1_BUSY (0x1 << 6)
519 #define RT5645_PDM_PATTERN (0x1 << 5)
520 #define RT5645_PDM_GAIN (0x1 << 4)
540 #define RT5645_M_MM_L_RM_L (0x1 << 6)
542 #define RT5645_M_IN_L_RM_L (0x1 << 5)
544 #define RT5645_M_HP_L_RM_L (0x1 << 4)
546 #define RT5645_M_BST3_RM_L (0x1 << 3)
548 #define RT5645_M_BST2_RM_L (0x1 << 2)
550 #define RT5645_M_BST1_RM_L (0x1 << 1)
552 #define RT5645_M_OM_L_RM_L (0x1)
572 #define RT5645_M_MM_R_RM_R (0x1 << 6)
574 #define RT5645_M_IN_R_RM_R (0x1 << 5)
576 #define RT5645_M_HP_R_RM_R (0x1 << 4)
578 #define RT5645_M_BST3_RM_R (0x1 << 3)
580 #define RT5645_M_BST2_RM_R (0x1 << 2)
582 #define RT5645_M_BST1_RM_R (0x1 << 1)
584 #define RT5645_M_OM_R_RM_R (0x1)
588 #define RT5645_M_BST1_HV (0x1 << 4)
590 #define RT5645_M_BST2_HV (0x1 << 4)
592 #define RT5645_M_BST3_HV (0x1 << 3)
594 #define RT5645_M_IN_HV (0x1 << 2)
596 #define RT5645_M_DAC2_HV (0x1 << 1)
598 #define RT5645_M_DAC1_HV (0x1 << 0)
602 #define RT5645_M_DAC1_HM (0x1 << 14)
604 #define RT5645_M_HPVOL_HM (0x1 << 13)
606 #define RT5645_IRQ_PSV_MODE (0x1 << 12)
619 #define RT5645_M_BST1_L_SM_L (0x1 << 5)
621 #define RT5645_M_BST3_L_SM_L (0x1 << 4)
623 #define RT5645_M_IN_L_SM_L (0x1 << 3)
625 #define RT5645_M_DAC_L2_SM_L (0x1 << 2)
627 #define RT5645_M_DAC_L1_SM_L (0x1 << 1)
641 #define RT5645_M_BST2_R_SM_R (0x1 << 5)
643 #define RT5645_M_BST3_R_SM_R (0x1 << 4)
645 #define RT5645_M_IN_R_SM_R (0x1 << 3)
647 #define RT5645_M_DAC_R2_SM_R (0x1 << 2)
649 #define RT5645_M_DAC_R1_SM_R (0x1 << 1)
653 #define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
655 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
657 #define RT5645_M_SV_L_SPM_L (0x1 << 13)
659 #define RT5645_M_SV_R_SPM_L (0x1 << 12)
661 #define RT5645_M_BST3_SPM_L (0x1 << 11)
663 #define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
665 #define RT5645_M_BST3_SPM_R (0x1 << 1)
667 #define RT5645_M_SV_R_SPM_R (0x1 << 0)
675 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
677 #define RT5645_M_OV_L_MM (0x1 << 9)
679 #define RT5645_M_DAC_L2_MA (0x1 << 8)
681 #define RT5645_M_BST2_MM (0x1 << 4)
683 #define RT5645_M_DAC_R1_MM (0x1 << 3)
685 #define RT5645_M_DAC_R2_MM (0x1 << 2)
687 #define RT5645_M_DAC_L2_MM (0x1 << 1)
689 #define RT5645_M_BST3_MM (0x1 << 0)
713 #define RT5645_M_BST3_OM_L (0x1 << 4)
715 #define RT5645_M_BST1_OM_L (0x1 << 3)
717 #define RT5645_M_IN_L_OM_L (0x1 << 2)
719 #define RT5645_M_DAC_L2_OM_L (0x1 << 1)
721 #define RT5645_M_DAC_L1_OM_L (0x1)
745 #define RT5645_M_BST3_OM_R (0x1 << 4)
747 #define RT5645_M_BST2_OM_R (0x1 << 3)
749 #define RT5645_M_IN_R_OM_R (0x1 << 2)
751 #define RT5645_M_DAC_R2_OM_R (0x1 << 1)
753 #define RT5645_M_DAC_R1_OM_R (0x1)
757 #define RT5645_M_DAC_L1_LM (0x1 << 15)
759 #define RT5645_M_DAC_R1_LM (0x1 << 14)
761 #define RT5645_M_OV_L_LM (0x1 << 13)
763 #define RT5645_M_OV_R_LM (0x1 << 12)
765 #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
769 #define RT5645_PWR_I2S1 (0x1 << 15)
771 #define RT5645_PWR_I2S2 (0x1 << 14)
773 #define RT5645_PWR_I2S3 (0x1 << 13)
775 #define RT5645_PWR_DAC_L1 (0x1 << 12)
777 #define RT5645_PWR_DAC_R1 (0x1 << 11)
779 #define RT5645_PWR_CLS_D_R (0x1 << 9)
781 #define RT5645_PWR_CLS_D_L (0x1 << 8)
783 #define RT5645_PWR_DAC_L2 (0x1 << 7)
785 #define RT5645_PWR_DAC_R2 (0x1 << 6)
787 #define RT5645_PWR_ADC_L (0x1 << 2)
789 #define RT5645_PWR_ADC_R (0x1 << 1)
791 #define RT5645_PWR_CLS_D (0x1)
795 #define RT5645_PWR_ADC_S1F (0x1 << 15)
797 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
799 #define RT5645_PWR_ADC_MF_R (0x1 << 13)
801 #define RT5645_PWR_I2S_DSP (0x1 << 12)
803 #define RT5645_PWR_DAC_S1F (0x1 << 11)
805 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
807 #define RT5645_PWR_DAC_MF_R (0x1 << 9)
809 #define RT5645_PWR_PDM1 (0x1 << 7)
811 #define RT5645_PWR_PDM2 (0x1 << 6)
813 #define RT5645_PWR_IPTV (0x1 << 1)
815 #define RT5645_PWR_PAD (0x1)
819 #define RT5645_PWR_VREF1 (0x1 << 15)
821 #define RT5645_PWR_FV1 (0x1 << 14)
823 #define RT5645_PWR_MB (0x1 << 13)
825 #define RT5645_PWR_LM (0x1 << 12)
827 #define RT5645_PWR_BG (0x1 << 11)
829 #define RT5645_PWR_MA (0x1 << 10)
831 #define RT5645_PWR_HP_L (0x1 << 7)
833 #define RT5645_PWR_HP_R (0x1 << 6)
835 #define RT5645_PWR_HA (0x1 << 5)
837 #define RT5645_PWR_VREF2 (0x1 << 4)
839 #define RT5645_PWR_FV2 (0x1 << 3)
845 #define RT5645_PWR_BST1 (0x1 << 15)
847 #define RT5645_PWR_BST2 (0x1 << 14)
849 #define RT5645_PWR_BST3 (0x1 << 13)
851 #define RT5645_PWR_BST4 (0x1 << 12)
853 #define RT5645_PWR_MB1 (0x1 << 11)
855 #define RT5645_PWR_MB2 (0x1 << 10)
857 #define RT5645_PWR_PLL (0x1 << 9)
859 #define RT5645_PWR_BST2_P (0x1 << 5)
861 #define RT5645_PWR_BST3_P (0x1 << 4)
863 #define RT5645_PWR_BST4_P (0x1 << 3)
865 #define RT5645_PWR_JD1 (0x1 << 2)
867 #define RT5645_PWR_JD (0x1 << 1)
871 #define RT5645_PWR_OM_L (0x1 << 15)
873 #define RT5645_PWR_OM_R (0x1 << 14)
875 #define RT5645_PWR_SM_L (0x1 << 13)
877 #define RT5645_PWR_SM_R (0x1 << 12)
879 #define RT5645_PWR_RM_L (0x1 << 11)
881 #define RT5645_PWR_RM_R (0x1 << 10)
883 #define RT5645_PWR_MM (0x1 << 8)
885 #define RT5645_PWR_HM_L (0x1 << 7)
887 #define RT5645_PWR_HM_R (0x1 << 6)
889 #define RT5645_PWR_LDO2 (0x1 << 1)
893 #define RT5645_PWR_SV_L (0x1 << 15)
895 #define RT5645_PWR_SV_R (0x1 << 14)
897 #define RT5645_PWR_HV_L (0x1 << 11)
899 #define RT5645_PWR_HV_R (0x1 << 10)
901 #define RT5645_PWR_IN_L (0x1 << 9)
903 #define RT5645_PWR_IN_R (0x1 << 8)
905 #define RT5645_PWR_MIC_DET (0x1 << 5)
909 #define RT5645_I2S_MS_MASK (0x1 << 15)
912 #define RT5645_I2S_MS_S (0x1 << 15)
916 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
921 #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
923 #define RT5645_I2S_BP_MASK (0x1 << 7)
926 #define RT5645_I2S_BP_INV (0x1 << 7)
930 #define RT5645_I2S_DL_20 (0x1 << 2)
936 #define RT5645_I2S_DF_LEFT (0x1)
941 #define RT5645_I2S2_SDI_MASK (0x1 << 6)
944 #define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
950 #define RT5645_I2S_PD1_2 (0x1 << 12)
957 #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
960 #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
964 #define RT5645_I2S_PD2_2 (0x1 << 8)
971 #define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
974 #define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
978 #define RT5645_I2S_PD3_2 (0x1 << 4)
988 #define RT5645_DAC_OSR_64 (0x1 << 2)
994 #define RT5645_ADC_OSR_64 (0x1)
1002 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1008 #define RT5645_ADC_R_OSR_64 (0x1 << 12)
1011 #define RT5645_DAHPF_EN (0x1 << 11)
1013 #define RT5645_ADHPF_EN (0x1 << 10)
1017 #define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1020 #define RT5645_DMIC_1_EN (0x1 << 15)
1021 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1024 #define RT5645_DMIC_2_EN (0x1 << 14)
1025 #define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1028 #define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1029 #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1032 #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1036 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1039 #define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
1042 #define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
1043 #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1046 #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1049 #define RT5645_DMIC_3_EN_MASK (0x1 << 4)
1052 #define RT5645_DMIC_3_EN (0x1 << 4)
1056 #define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
1067 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1072 #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1076 #define RT5645_PLL1_PD_MASK (0x1 << 3)
1079 #define RT5645_PLL1_PD_2 (0x1 << 3)
1095 #define RT5645_PLL_M_BP (0x1 << 11)
1099 #define RT5645_STO_T_MASK (0x1 << 15)
1102 #define RT5645_STO_T_LRCK1 (0x1 << 15)
1103 #define RT5645_M1_T_MASK (0x1 << 14)
1106 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1107 #define RT5645_I2S2_F_MASK (0x1 << 12)
1110 #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1111 #define RT5645_DMIC_1_M_MASK (0x1 << 9)
1114 #define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1115 #define RT5645_DMIC_2_M_MASK (0x1 << 8)
1118 #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1122 #define RT5645_CLK_SEL_I2S1_ASRC (0x1)
1149 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1152 #define RT5645_HP_OVCD_EN (0x1 << 10)
1156 #define RT5645_HP_OC_TH_105 (0x1 << 8)
1161 #define RT5645_CLSD_OC_MASK (0x1 << 9)
1164 #define RT5645_CLSD_OC_PD (0x1 << 9)
1165 #define RT5645_AUTO_PD_MASK (0x1 << 8)
1168 #define RT5645_AUTO_PD_EN (0x1 << 8)
1175 #define RT5645_CLSD_OM_MASK (0x1 << 11)
1178 #define RT5645_CLSD_OM_STO (0x1 << 11)
1179 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1182 #define RT5645_CLSD_SCH_S (0x1 << 10)
1185 #define RT5645_SMT_TRIG_MASK (0x1 << 15)
1188 #define RT5645_SMT_TRIG_EN (0x1 << 15)
1189 #define RT5645_HP_L_SMT_MASK (0x1 << 9)
1192 #define RT5645_HP_L_SMT_EN (0x1 << 9)
1193 #define RT5645_HP_R_SMT_MASK (0x1 << 8)
1196 #define RT5645_HP_R_SMT_EN (0x1 << 8)
1197 #define RT5645_HP_CD_PD_MASK (0x1 << 7)
1200 #define RT5645_HP_CD_PD_EN (0x1 << 7)
1201 #define RT5645_RSTN_MASK (0x1 << 6)
1204 #define RT5645_RSTN_EN (0x1 << 6)
1205 #define RT5645_RSTP_MASK (0x1 << 5)
1208 #define RT5645_RSTP_EN (0x1 << 5)
1209 #define RT5645_HP_CO_MASK (0x1 << 4)
1212 #define RT5645_HP_CO_EN (0x1 << 4)
1213 #define RT5645_HP_CP_MASK (0x1 << 3)
1216 #define RT5645_HP_CP_PU (0x1 << 3)
1217 #define RT5645_HP_SG_MASK (0x1 << 2)
1220 #define RT5645_HP_SG_EN (0x1 << 2)
1221 #define RT5645_HP_DP_MASK (0x1 << 1)
1224 #define RT5645_HP_DP_PU (0x1 << 1)
1225 #define RT5645_HP_CB_MASK (0x1)
1228 #define RT5645_HP_CB_PU (0x1)
1231 #define RT5645_DEPOP_MASK (0x1 << 13)
1234 #define RT5645_DEPOP_MAN (0x1 << 13)
1235 #define RT5645_RAMP_MASK (0x1 << 12)
1238 #define RT5645_RAMP_EN (0x1 << 12)
1239 #define RT5645_BPS_MASK (0x1 << 11)
1242 #define RT5645_BPS_EN (0x1 << 11)
1243 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1246 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1250 #define RT5645_MRES_25MO (0x1 << 8)
1253 #define RT5645_VLO_MASK (0x1 << 7)
1256 #define RT5645_VLO_32V (0x1 << 7)
1257 #define RT5645_DIG_DP_MASK (0x1 << 6)
1260 #define RT5645_DIG_DP_EN (0x1 << 6)
1283 #define RT5645_PVDD_DET_MASK (0x1 << 15)
1286 #define RT5645_PVDD_DET_EN (0x1 << 15)
1287 #define RT5645_SPK_AG_MASK (0x1 << 14)
1290 #define RT5645_SPK_AG_EN (0x1 << 14)
1293 #define RT5645_MIC1_BS_MASK (0x1 << 15)
1296 #define RT5645_MIC1_BS_75AV (0x1 << 15)
1297 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1300 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1301 #define RT5645_MIC1_CLK_MASK (0x1 << 13)
1304 #define RT5645_MIC1_CLK_EN (0x1 << 13)
1305 #define RT5645_MIC2_CLK_MASK (0x1 << 12)
1308 #define RT5645_MIC2_CLK_EN (0x1 << 12)
1309 #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1312 #define RT5645_MIC1_OVCD_EN (0x1 << 11)
1316 #define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
1318 #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1321 #define RT5645_MIC2_OVCD_EN (0x1 << 8)
1325 #define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1327 #define RT5645_PWR_MB_MASK (0x1 << 5)
1330 #define RT5645_PWR_MB_PU (0x1 << 5)
1331 #define RT5645_PWR_CLK25M_MASK (0x1 << 4)
1334 #define RT5645_PWR_CLK25M_PU (0x1 << 4)
1336 #define RT5645_IRQ_CLK_INT (0x1 << 3)
1339 #define RT5645_JD1_MODE_1 (0x1 << 0)
1347 #define RT5645_EQ_SRC_MASK (0x1 << 15)
1350 #define RT5645_EQ_SRC_ADC (0x1 << 15)
1351 #define RT5645_EQ_UPD (0x1 << 14)
1353 #define RT5645_EQ_CD_MASK (0x1 << 13)
1356 #define RT5645_EQ_CD_EN (0x1 << 13)
1360 #define RT5645_EQ_DITH_LSB (0x1 << 8)
1365 #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1368 #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1369 #define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
1372 #define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
1373 #define RT5645_EQ_HPF2_MASK (0x1 << 6)
1376 #define RT5645_EQ_HPF2_EN (0x1 << 6)
1377 #define RT5645_EQ_HPF1_MASK (0x1 << 5)
1380 #define RT5645_EQ_HPF1_EN (0x1 << 5)
1381 #define RT5645_EQ_BPF4_MASK (0x1 << 4)
1384 #define RT5645_EQ_BPF4_EN (0x1 << 4)
1385 #define RT5645_EQ_BPF3_MASK (0x1 << 3)
1388 #define RT5645_EQ_BPF3_EN (0x1 << 3)
1389 #define RT5645_EQ_BPF2_MASK (0x1 << 2)
1392 #define RT5645_EQ_BPF2_EN (0x1 << 2)
1393 #define RT5645_EQ_BPF1_MASK (0x1 << 1)
1396 #define RT5645_EQ_BPF1_EN (0x1 << 1)
1397 #define RT5645_EQ_LPF_MASK (0x1)
1400 #define RT5645_EQ_LPF_EN (0x1)
1404 #define RT5645_MT_MASK (0x1 << 15)
1407 #define RT5645_MT_EN (0x1 << 15)
1410 #define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1413 #define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1414 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1417 #define RT5645_DRC_AGC_EN (0x1 << 14)
1418 #define RT5645_DRC_AGC_UPD (0x1 << 13)
1424 #define RT5645_DRC_AGC_R_48K (0x1 << 5)
1436 #define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
1439 #define RT5645_DRC_AGC_CP_EN (0x1 << 7)
1443 #define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
1454 #define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1457 #define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1458 #define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
1461 #define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
1466 #define RT5645_ANC_M_MASK (0x1 << 15)
1469 #define RT5645_ANC_M_REV (0x1 << 15)
1470 #define RT5645_ANC_MASK (0x1 << 14)
1473 #define RT5645_ANC_EN (0x1 << 14)
1477 #define RT5645_ANC_MD_67MS (0x1 << 12)
1480 #define RT5645_ANC_SN_MASK (0x1 << 11)
1483 #define RT5645_ANC_SN_EN (0x1 << 11)
1484 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1487 #define RT5645_ANC_CLK_REG (0x1 << 10)
1491 #define RT5645_ANC_ZCD_T1 (0x1 << 8)
1494 #define RT5645_ANC_CS_MASK (0x1 << 7)
1497 #define RT5645_ANC_CS_EN (0x1 << 7)
1498 #define RT5645_ANC_SW_MASK (0x1 << 6)
1501 #define RT5645_ANC_SW_AUTO (0x1 << 6)
1516 #define RT5645_ANC_CD_MASK (0x1 << 6)
1519 #define RT5645_ANC_CD_IND (0x1 << 6)
1527 #define RT5645_JD_GPIO1 (0x1 << 13)
1533 #define RT5645_JD_HP_MASK (0x1 << 11)
1536 #define RT5645_JD_HP_EN (0x1 << 11)
1537 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1540 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1541 #define RT5645_JD_SPL_MASK (0x1 << 9)
1544 #define RT5645_JD_SPL_EN (0x1 << 9)
1545 #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1548 #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1549 #define RT5645_JD_SPR_MASK (0x1 << 7)
1552 #define RT5645_JD_SPR_EN (0x1 << 7)
1553 #define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1556 #define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1557 #define RT5645_JD_MO_MASK (0x1 << 5)
1560 #define RT5645_JD_MO_EN (0x1 << 5)
1561 #define RT5645_JD_MO_TRG_MASK (0x1 << 4)
1564 #define RT5645_JD_MO_TRG_HI (0x1 << 4)
1565 #define RT5645_JD_LO_MASK (0x1 << 3)
1568 #define RT5645_JD_LO_EN (0x1 << 3)
1569 #define RT5645_JD_LO_TRG_MASK (0x1 << 2)
1572 #define RT5645_JD_LO_TRG_HI (0x1 << 2)
1573 #define RT5645_JD1_IN4P_MASK (0x1 << 1)
1576 #define RT5645_JD1_IN4P_EN (0x1 << 1)
1577 #define RT5645_JD2_IN4N_MASK (0x1)
1580 #define RT5645_JD2_IN4N_EN (0x1)
1586 #define RT5645_ANC_DET_MB1 (0x1 << 4)
1589 #define RT5645_AD_TRG_MASK (0x1 << 3)
1592 #define RT5645_AD_TRG_HI (0x1 << 3)
1596 #define RT5645_ANCM_DET_MB1 (0x1 << 4)
1599 #define RT5645_AMD_TRG_MASK (0x1 << 3)
1602 #define RT5645_AMD_TRG_HI (0x1 << 3)
1605 #define RT5645_IRQ_JD_MASK (0x1 << 15)
1608 #define RT5645_IRQ_JD_NOR (0x1 << 15)
1609 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1612 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1613 #define RT5645_JD_STKY_MASK (0x1 << 13)
1616 #define RT5645_JD_STKY_EN (0x1 << 13)
1617 #define RT5645_OT_STKY_MASK (0x1 << 12)
1620 #define RT5645_OT_STKY_EN (0x1 << 12)
1621 #define RT5645_JD_P_MASK (0x1 << 11)
1624 #define RT5645_JD_P_INV (0x1 << 11)
1625 #define RT5645_OT_P_MASK (0x1 << 10)
1628 #define RT5645_OT_P_INV (0x1 << 10)
1629 #define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
1630 #define RT5645_JD_1_1_MASK (0x1 << 7)
1633 #define RT5645_JD_1_1_INV (0x1 << 7)
1636 #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1639 #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1640 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1643 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1644 #define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1647 #define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1648 #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1651 #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1652 #define RT5645_MB1_OC_P_MASK (0x1 << 7)
1655 #define RT5645_MB1_OC_P_INV (0x1 << 7)
1656 #define RT5645_MB2_OC_P_MASK (0x1 << 6)
1659 #define RT5645_MB2_OC_P_INV (0x1 << 6)
1660 #define RT5645_MB1_OC_CLR (0x1 << 3)
1662 #define RT5645_MB2_OC_CLR (0x1 << 2)
1666 #define RT5645_GP1_PIN_MASK (0x1 << 15)
1669 #define RT5645_GP1_PIN_IRQ (0x1 << 15)
1670 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1673 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1677 #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1679 #define RT5645_GP4_PIN_MASK (0x1 << 11)
1682 #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1683 #define RT5645_DP_SIG_MASK (0x1 << 10)
1686 #define RT5645_DP_SIG_AP (0x1 << 10)
1687 #define RT5645_GPIO_M_MASK (0x1 << 9)
1690 #define RT5645_GPIO_M_PH (0x1 << 9)
1691 #define RT5645_I2S2_SEL (0x1 << 8)
1693 #define RT5645_GP5_PIN_MASK (0x1 << 7)
1696 #define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
1697 #define RT5645_GP6_PIN_MASK (0x1 << 6)
1700 #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1701 #define RT5645_I2S2_DAC_PIN_MASK (0x1 << 4)
1704 #define RT5645_I2S2_DAC_PIN_GPIO (0x1 << 4)
1705 #define RT5645_GP8_PIN_MASK (0x1 << 3)
1708 #define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
1709 #define RT5645_GP12_PIN_MASK (0x1 << 2)
1712 #define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
1713 #define RT5645_GP11_PIN_MASK (0x1 << 1)
1716 #define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
1717 #define RT5645_GP10_PIN_MASK (0x1)
1720 #define RT5645_GP10_PIN_DMIC2_SDA (0x1)
1723 #define RT5645_GP4_PF_MASK (0x1 << 11)
1726 #define RT5645_GP4_PF_OUT (0x1 << 11)
1727 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1730 #define RT5645_GP4_OUT_HI (0x1 << 10)
1731 #define RT5645_GP4_P_MASK (0x1 << 9)
1734 #define RT5645_GP4_P_INV (0x1 << 9)
1735 #define RT5645_GP3_PF_MASK (0x1 << 8)
1738 #define RT5645_GP3_PF_OUT (0x1 << 8)
1739 #define RT5645_GP3_OUT_MASK (0x1 << 7)
1742 #define RT5645_GP3_OUT_HI (0x1 << 7)
1743 #define RT5645_GP3_P_MASK (0x1 << 6)
1746 #define RT5645_GP3_P_INV (0x1 << 6)
1747 #define RT5645_GP2_PF_MASK (0x1 << 5)
1750 #define RT5645_GP2_PF_OUT (0x1 << 5)
1751 #define RT5645_GP2_OUT_MASK (0x1 << 4)
1754 #define RT5645_GP2_OUT_HI (0x1 << 4)
1755 #define RT5645_GP2_P_MASK (0x1 << 3)
1758 #define RT5645_GP2_P_INV (0x1 << 3)
1759 #define RT5645_GP1_PF_MASK (0x1 << 2)
1762 #define RT5645_GP1_PF_OUT (0x1 << 2)
1763 #define RT5645_GP1_OUT_MASK (0x1 << 1)
1766 #define RT5645_GP1_OUT_HI (0x1 << 1)
1767 #define RT5645_GP1_P_MASK (0x1)
1770 #define RT5645_GP1_P_INV (0x1)
1775 #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1778 #define RT5645_SEQ1_ST_FIN (0x1 << 11)
1779 #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1782 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1783 #define RT5645_REG_LV_MASK (0x1 << 9)
1786 #define RT5645_REG_LV_PR (0x1 << 9)
1787 #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1799 #define RT5645_PROG_MASK (0x1 << 7)
1802 #define RT5645_PROG_EN (0x1 << 7)
1803 #define RT5645_SEQ1_PT_RUN (0x1 << 6)
1805 #define RT5645_SEQ2_PT_RUN (0x1 << 5)
1825 #define RT5645_SCB_SWAP_MASK (0x1 << 15)
1828 #define RT5645_SCB_SWAP_EN (0x1 << 15)
1829 #define RT5645_SCB_MASK (0x1 << 14)
1832 #define RT5645_SCB_EN (0x1 << 14)
1835 #define RT5645_BB_MASK (0x1 << 15)
1838 #define RT5645_BB_EN (0x1 << 15)
1842 #define RT5645_BB_CT_B (0x1 << 12)
1845 #define RT5645_M_BB_L_MASK (0x1 << 9)
1847 #define RT5645_M_BB_R_MASK (0x1 << 8)
1849 #define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
1851 #define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1858 #define RT5645_M_MP3_L_MASK (0x1 << 15)
1860 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1862 #define RT5645_M_MP3_MASK (0x1 << 13)
1865 #define RT5645_M_MP3_EN (0x1 << 13)
1868 #define RT5645_MP3_HLP_MASK (0x1 << 7)
1871 #define RT5645_MP3_HLP_EN (0x1 << 7)
1872 #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1874 #define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
1878 #define RT5645_MP3_WT_MASK (0x1 << 13)
1881 #define RT5645_MP3_WT_1_2 (0x1 << 13)
1888 #define RT5645_3D_CF_MASK (0x1 << 15)
1891 #define RT5645_3D_CF_EN (0x1 << 15)
1892 #define RT5645_3D_HP_MASK (0x1 << 14)
1895 #define RT5645_3D_HP_EN (0x1 << 14)
1896 #define RT5645_3D_BT_MASK (0x1 << 13)
1899 #define RT5645_3D_BT_EN (0x1 << 13)
1902 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1905 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1906 #define RT5645_M_3D_HRTF_MASK (0x1 << 9)
1908 #define RT5645_M_3D_D2H_MASK (0x1 << 8)
1910 #define RT5645_M_3D_D2R_MASK (0x1 << 7)
1912 #define RT5645_M_3D_REVB_MASK (0x1 << 6)
1916 #define RT5645_2ND_HPF_MASK (0x1 << 15)
1919 #define RT5645_2ND_HPF_EN (0x1 << 15)
1922 #define RT5645_1ST_HPF_MASK (0x1 << 11)
1925 #define RT5645_1ST_HPF_EN (0x1 << 11)
1933 #define RT5645_ZD_F_ZC_IM (0x1 << 4)
1938 #define RT5645_SI_DAC_MASK (0x1 << 11)
1941 #define RT5645_SI_DAC_TEST (0x1 << 11)
1942 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1945 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1946 #define RT5645_DC_CAL_MASK (0x1 << 9)
1949 #define RT5645_DC_CAL_EN (0x1 << 9)
1952 #define RT5645_HPD_PS_MASK (0x1 << 5)
1955 #define RT5645_HPD_PS_EN (0x1 << 5)
1956 #define RT5645_CAL_M_MASK (0x1 << 4)
1959 #define RT5645_CAL_M_CAL (0x1 << 4)
1960 #define RT5645_CAL_MASK (0x1 << 3)
1963 #define RT5645_CAL_EN (0x1 << 3)
1964 #define RT5645_CAL_TEST_MASK (0x1 << 2)
1967 #define RT5645_CAL_TEST_EN (0x1 << 2)
1971 #define RT5645_CAL_P_CAL (0x1)
1975 #define RT5645_SV_MASK (0x1 << 15)
1978 #define RT5645_SV_EN (0x1 << 15)
1979 #define RT5645_SPO_SV_MASK (0x1 << 14)
1982 #define RT5645_SPO_SV_EN (0x1 << 14)
1983 #define RT5645_OUT_SV_MASK (0x1 << 13)
1986 #define RT5645_OUT_SV_EN (0x1 << 13)
1987 #define RT5645_HP_SV_MASK (0x1 << 12)
1990 #define RT5645_HP_SV_EN (0x1 << 12)
1991 #define RT5645_ZCD_DIG_MASK (0x1 << 11)
1994 #define RT5645_ZCD_DIG_EN (0x1 << 11)
1995 #define RT5645_ZCD_MASK (0x1 << 10)
1998 #define RT5645_ZCD_PU (0x1 << 10)
2001 #define RT5645_M_ZCD_RM_L (0x1 << 9)
2002 #define RT5645_M_ZCD_RM_R (0x1 << 8)
2003 #define RT5645_M_ZCD_SM_L (0x1 << 7)
2004 #define RT5645_M_ZCD_SM_R (0x1 << 6)
2005 #define RT5645_M_ZCD_OM_L (0x1 << 5)
2006 #define RT5645_M_ZCD_OM_R (0x1 << 4)
2011 #define RT5645_ZCD_HP_MASK (0x1 << 15)
2014 #define RT5645_ZCD_HP_EN (0x1 << 15)
2022 #define RT5645_3D_SPK_MASK (0x1 << 15)
2025 #define RT5645_3D_SPK_EN (0x1 << 15)
2034 #define RT5645_WND_MASK (0x1 << 15)
2037 #define RT5645_WND_EN (0x1 << 15)
2060 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2062 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2073 #define RT5645_DP_SPK_MASK (0x1 << 10)
2076 #define RT5645_DP_SPK_EN (0x1 << 10)
2088 #define RT5645_JD_CBJ_EN (0x1 << 7)
2089 #define RT5645_JD_CBJ_POL (0x1 << 6)
2095 #define RT5645_JD_F_JD1_1 (0x1)
2103 #define RT5645_RST_DSP (0x1 << 13)
2104 #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2106 #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2108 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2110 #define RT5645_DIG_GATE_CTRL 0x1
2113 #define RT5645_RXDC_SRC_MASK (0x1 << 7)
2115 #define RT5645_RXDC_SRC_MONO (0x1 << 7)
2117 #define RT5645_MICBIAS1_POW_CTRL_SEL_MASK (0x1 << 5)
2119 #define RT5645_MICBIAS1_POW_CTRL_SEL_M (0x1 << 5)
2120 #define RT5645_MICBIAS2_POW_CTRL_SEL_MASK (0x1 << 4)
2122 #define RT5645_MICBIAS2_POW_CTRL_SEL_M (0x1 << 4)
2123 #define RT5645_RXDP2_SEL_MASK (0x1 << 3)
2125 #define RT5645_RXDP2_SEL_ADC (0x1 << 3)
2129 #define RT5645_JD_PSV_MODE (0x1 << 12)
2130 #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
2133 #define RT5645_DET_CLK_MODE1 (0x1 << 9)
2135 #define RT5645_MICINDET_MANU (0x1 << 7)
2136 #define RT5645_RING2_SLEEVE_GND (0x1 << 5)
2192 RT5645_DA_STEREO_FILTER = 0x1,
2193 RT5645_DA_MONO_L_FILTER = (0x1 << 1),
2194 RT5645_DA_MONO_R_FILTER = (0x1 << 2),
2195 RT5645_AD_STEREO_FILTER = (0x1 << 3),
2196 RT5645_AD_MONO_L_FILTER = (0x1 << 4),
2197 RT5645_AD_MONO_R_FILTER = (0x1 << 5),