Lines Matching refs:x1
298 #define RT5677_L_MUTE (0x1 << 15)
300 #define RT5677_VOL_L_MUTE (0x1 << 14)
302 #define RT5677_R_MUTE (0x1 << 7)
304 #define RT5677_VOL_R_MUTE (0x1 << 6)
312 #define RT5677_LOUT1_L_MUTE (0x1 << 15)
314 #define RT5677_LOUT1_L_DF (0x1 << 14)
316 #define RT5677_LOUT2_L_MUTE (0x1 << 13)
318 #define RT5677_LOUT2_L_DF (0x1 << 12)
320 #define RT5677_LOUT3_L_MUTE (0x1 << 11)
322 #define RT5677_LOUT3_L_DF (0x1 << 10)
324 #define RT5677_LOUT1_ENH_DRV (0x1 << 9)
326 #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
328 #define RT5677_LOUT3_ENH_DRV (0x1 << 7)
336 #define RT5677_IN_DF1 (0x1 << 7)
338 #define RT5677_IN_DF2 (0x1 << 6)
342 #define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
345 #define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
346 #define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
349 #define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
350 #define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
353 #define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
357 #define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
377 #define RT5677_ST_HPF_PATH (0x1 << 12)
381 #define RT5677_ST_EN (0x1 << 6)
383 #define RT5677_ST_GAIN (0x1 << 5)
395 #define RT5677_M_DAC4_L_VOL (0x1 << 15)
399 #define RT5677_M_DAC4_R_VOL (0x1 << 11)
403 #define RT5677_M_DAC3_L_VOL (0x1 << 7)
407 #define RT5677_M_DAC3_R_VOL (0x1 << 3)
437 #define RT5677_M_DAC2_L_VOL (0x1 << 7)
441 #define RT5677_M_DAC2_R_VOL (0x1 << 3)
513 #define RT5677_M_STO4_ADC_L2 (0x1 << 15)
515 #define RT5677_M_STO4_ADC_L1 (0x1 << 14)
523 #define RT5677_M_STO4_ADC_R1 (0x1 << 7)
525 #define RT5677_M_STO4_ADC_R2 (0x1 << 6)
529 #define RT5677_M_STO3_ADC_L2 (0x1 << 15)
531 #define RT5677_M_STO3_ADC_L1 (0x1 << 14)
539 #define RT5677_M_STO3_ADC_R1 (0x1 << 7)
541 #define RT5677_M_STO3_ADC_R2 (0x1 << 6)
545 #define RT5677_M_STO2_ADC_L2 (0x1 << 15)
547 #define RT5677_M_STO2_ADC_L1 (0x1 << 14)
555 #define RT5677_M_STO2_ADC_R1 (0x1 << 7)
557 #define RT5677_M_STO2_ADC_R2 (0x1 << 6)
559 #define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
562 #define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
565 #define RT5677_M_STO1_ADC_L2 (0x1 << 15)
567 #define RT5677_M_STO1_ADC_L1 (0x1 << 14)
575 #define RT5677_M_STO1_ADC_R1 (0x1 << 7)
577 #define RT5677_M_STO1_ADC_R2 (0x1 << 6)
581 #define RT5677_M_MONO_ADC_L2 (0x1 << 15)
583 #define RT5677_M_MONO_ADC_L1 (0x1 << 14)
591 #define RT5677_M_MONO_ADC_R1 (0x1 << 7)
593 #define RT5677_M_MONO_ADC_R2 (0x1 << 6)
603 #define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
605 #define RT5677_M_DAC1_L (0x1 << 14)
609 #define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
611 #define RT5677_M_DAC1_R (0x1 << 6)
617 #define RT5677_M_ST_DAC1_L (0x1 << 15)
619 #define RT5677_M_DAC1_L_STO_L (0x1 << 13)
621 #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
623 #define RT5677_M_DAC2_L_STO_L (0x1 << 11)
625 #define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
627 #define RT5677_M_DAC1_R_STO_L (0x1 << 9)
629 #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
631 #define RT5677_M_ST_DAC1_R (0x1 << 7)
633 #define RT5677_M_DAC1_R_STO_R (0x1 << 5)
635 #define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
637 #define RT5677_M_DAC2_R_STO_R (0x1 << 3)
639 #define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
641 #define RT5677_M_DAC1_L_STO_R (0x1 << 1)
643 #define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
647 #define RT5677_M_ST_DAC2_L (0x1 << 15)
649 #define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
651 #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
653 #define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
655 #define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
657 #define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
659 #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
661 #define RT5677_M_ST_DAC2_R (0x1 << 7)
663 #define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
665 #define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
667 #define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
669 #define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
671 #define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
673 #define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
677 #define RT5677_M_STO_L_DD1_L (0x1 << 15)
679 #define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
681 #define RT5677_M_MONO_L_DD1_L (0x1 << 13)
683 #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
685 #define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
687 #define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
689 #define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
691 #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
693 #define RT5677_M_STO_R_DD1_R (0x1 << 7)
695 #define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
697 #define RT5677_M_MONO_R_DD1_R (0x1 << 5)
699 #define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
701 #define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
703 #define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
705 #define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
707 #define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
711 #define RT5677_M_STO_L_DD2_L (0x1 << 15)
713 #define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
715 #define RT5677_M_MONO_L_DD2_L (0x1 << 13)
717 #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
719 #define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
721 #define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
723 #define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
725 #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
727 #define RT5677_M_STO_R_DD2_R (0x1 << 7)
729 #define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
731 #define RT5677_M_MONO_R_DD2_R (0x1 << 5)
733 #define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
735 #define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
737 #define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
739 #define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
741 #define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
761 #define RT5677_M_PDM1_L (0x1 << 15)
765 #define RT5677_M_PDM1_R (0x1 << 11)
769 #define RT5677_M_PDM2_L (0x1 << 7)
773 #define RT5677_M_PDM2_R (0x1 << 3)
779 #define RT5677_PDM2_PW_DOWN (0x1 << 7)
780 #define RT5677_PDM1_PW_DOWN (0x1 << 6)
781 #define RT5677_PDM2_BUSY (0x1 << 5)
782 #define RT5677_PDM1_BUSY (0x1 << 4)
783 #define RT5677_PDM_PATTERN (0x1 << 3)
784 #define RT5677_PDM_GAIN (0x1 << 2)
789 #define RT5677_PDM1_EXE (0x1 << 11)
790 #define RT5677_PDM1_I2C_CMD (0x1 << 10)
791 #define RT5677_PDM1_I2C_EXE (0x1 << 9)
792 #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
794 #define RT5677_PDM2_EXE (0x1 << 3)
795 #define RT5677_PDM2_I2C_CMD (0x1 << 2)
796 #define RT5677_PDM2_I2C_EXE (0x1 << 1)
797 #define RT5677_PDM2_I2C_BUSY (0x1 << 0)
800 #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12)
803 #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12)
846 #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12)
849 #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12)
892 #define RT5677_DMIC_1_EN_MASK (0x1 << 15)
895 #define RT5677_DMIC_1_EN (0x1 << 15)
896 #define RT5677_DMIC_2_EN_MASK (0x1 << 14)
899 #define RT5677_DMIC_2_EN (0x1 << 14)
900 #define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
903 #define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
904 #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
907 #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
908 #define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
911 #define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
912 #define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
915 #define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
916 #define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
919 #define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
920 #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
923 #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
926 #define RT5677_DMIC_3_EN_MASK (0x1 << 4)
929 #define RT5677_DMIC_3_EN (0x1 << 4)
930 #define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
933 #define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
934 #define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
937 #define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
938 #define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
941 #define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
944 #define RT5677_DMIC_4_EN_MASK (0x1 << 15)
947 #define RT5677_DMIC_4_EN (0x1 << 15)
948 #define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
951 #define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
952 #define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
955 #define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
956 #define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
959 #define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
960 #define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
963 #define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
964 #define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
967 #define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
968 #define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
971 #define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
972 #define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
975 #define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
976 #define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
979 #define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
982 #define RT5677_PWR_I2S1 (0x1 << 15)
984 #define RT5677_PWR_I2S2 (0x1 << 14)
986 #define RT5677_PWR_I2S3 (0x1 << 13)
988 #define RT5677_PWR_DAC1 (0x1 << 12)
990 #define RT5677_PWR_DAC2 (0x1 << 11)
992 #define RT5677_PWR_I2S4 (0x1 << 10)
994 #define RT5677_PWR_SLB (0x1 << 9)
996 #define RT5677_PWR_DAC3 (0x1 << 7)
998 #define RT5677_PWR_ADCFED2 (0x1 << 4)
1000 #define RT5677_PWR_ADCFED1 (0x1 << 3)
1002 #define RT5677_PWR_ADC_L (0x1 << 2)
1004 #define RT5677_PWR_ADC_R (0x1 << 1)
1006 #define RT5677_PWR_I2C_MASTER (0x1 << 0)
1010 #define RT5677_PWR_ADC_S1F (0x1 << 15)
1012 #define RT5677_PWR_ADC_MF_L (0x1 << 14)
1014 #define RT5677_PWR_ADC_MF_R (0x1 << 13)
1016 #define RT5677_PWR_DAC_S1F (0x1 << 12)
1018 #define RT5677_PWR_DAC_M2F_L (0x1 << 11)
1020 #define RT5677_PWR_DAC_M2F_R (0x1 << 10)
1022 #define RT5677_PWR_DAC_M3F_L (0x1 << 9)
1024 #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
1026 #define RT5677_PWR_DAC_M4F_L (0x1 << 7)
1028 #define RT5677_PWR_DAC_M4F_R (0x1 << 6)
1030 #define RT5677_PWR_ADC_S2F (0x1 << 5)
1032 #define RT5677_PWR_ADC_S3F (0x1 << 4)
1034 #define RT5677_PWR_ADC_S4F (0x1 << 3)
1036 #define RT5677_PWR_PDM1 (0x1 << 2)
1038 #define RT5677_PWR_PDM2 (0x1 << 1)
1042 #define RT5677_PWR_VREF1 (0x1 << 15)
1044 #define RT5677_PWR_FV1 (0x1 << 14)
1046 #define RT5677_PWR_MB (0x1 << 13)
1048 #define RT5677_PWR_LO1 (0x1 << 12)
1050 #define RT5677_PWR_BG (0x1 << 11)
1052 #define RT5677_PWR_LO2 (0x1 << 10)
1054 #define RT5677_PWR_LO3 (0x1 << 9)
1056 #define RT5677_PWR_VREF2 (0x1 << 8)
1058 #define RT5677_PWR_FV2 (0x1 << 7)
1066 #define RT5677_PWR_BST1 (0x1 << 15)
1068 #define RT5677_PWR_BST2 (0x1 << 14)
1070 #define RT5677_PWR_CLK_MB1 (0x1 << 13)
1072 #define RT5677_PWR_SLIM (0x1 << 12)
1074 #define RT5677_PWR_MB1 (0x1 << 11)
1076 #define RT5677_PWR_PP_MB1 (0x1 << 10)
1078 #define RT5677_PWR_PLL1 (0x1 << 9)
1080 #define RT5677_PWR_PLL2 (0x1 << 8)
1082 #define RT5677_PWR_CORE (0x1 << 7)
1084 #define RT5677_PWR_CLK_MB (0x1 << 6)
1086 #define RT5677_PWR_BST1_P (0x1 << 5)
1088 #define RT5677_PWR_BST2_P (0x1 << 4)
1090 #define RT5677_PWR_IPTV (0x1 << 3)
1092 #define RT5677_PWR_25M_CLK (0x1 << 1)
1094 #define RT5677_PWR_LDO1 (0x1 << 0)
1098 #define RT5677_PWR_SR7 (0x1 << 10)
1100 #define RT5677_PWR_SR6 (0x1 << 9)
1102 #define RT5677_PWR_SR5 (0x1 << 8)
1104 #define RT5677_PWR_SR4 (0x1 << 7)
1106 #define RT5677_PWR_SR3 (0x1 << 6)
1108 #define RT5677_PWR_SR2 (0x1 << 5)
1110 #define RT5677_PWR_SR1 (0x1 << 4)
1112 #define RT5677_PWR_SR0 (0x1 << 3)
1114 #define RT5677_PWR_MLT (0x1 << 2)
1116 #define RT5677_PWR_DSP (0x1 << 1)
1118 #define RT5677_PWR_DSP_CPU (0x1 << 0)
1122 #define RT5677_PWR_SR7_RDY (0x1 << 9)
1124 #define RT5677_PWR_SR6_RDY (0x1 << 8)
1126 #define RT5677_PWR_SR5_RDY (0x1 << 7)
1128 #define RT5677_PWR_SR4_RDY (0x1 << 6)
1130 #define RT5677_PWR_SR3_RDY (0x1 << 5)
1132 #define RT5677_PWR_SR2_RDY (0x1 << 4)
1134 #define RT5677_PWR_SR1_RDY (0x1 << 3)
1136 #define RT5677_PWR_SR0_RDY (0x1 << 2)
1138 #define RT5677_PWR_MLT_RDY (0x1 << 1)
1140 #define RT5677_PWR_DSP_RDY (0x1 << 0)
1144 #define RT5677_PWR_SLIM_ISO (0x1 << 11)
1146 #define RT5677_PWR_CORE_ISO (0x1 << 10)
1148 #define RT5677_PWR_DSP_ISO (0x1 << 9)
1150 #define RT5677_PWR_SR7_ISO (0x1 << 8)
1152 #define RT5677_PWR_SR6_ISO (0x1 << 7)
1154 #define RT5677_PWR_SR5_ISO (0x1 << 6)
1156 #define RT5677_PWR_SR4_ISO (0x1 << 5)
1158 #define RT5677_PWR_SR3_ISO (0x1 << 4)
1160 #define RT5677_PWR_SR2_ISO (0x1 << 3)
1162 #define RT5677_PWR_SR1_ISO (0x1 << 2)
1164 #define RT5677_PWR_SR0_ISO (0x1 << 1)
1166 #define RT5677_PWR_MLT_ISO (0x1 << 0)
1170 #define RT5677_I2S_MS_MASK (0x1 << 15)
1173 #define RT5677_I2S_MS_S (0x1 << 15)
1177 #define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
1182 #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1184 #define RT5677_I2S_BP_MASK (0x1 << 7)
1187 #define RT5677_I2S_BP_INV (0x1 << 7)
1191 #define RT5677_I2S_DL_20 (0x1 << 2)
1197 #define RT5677_I2S_DF_LEFT (0x1 << 0)
1205 #define RT5677_I2S_PD1_2 (0x1 << 12)
1212 #define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
1215 #define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
1219 #define RT5677_I2S_PD2_2 (0x1 << 8)
1226 #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
1229 #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
1233 #define RT5677_I2S_PD3_2 (0x1 << 4)
1240 #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
1243 #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
1247 #define RT5677_I2S_PD4_2 (0x1 << 0)
1259 #define RT5677_I2S_PD5_2 (0x1 << 12)
1269 #define RT5677_I2S_PD6_2 (0x1 << 8)
1279 #define RT5677_I2S_PD7_2 (0x1 << 4)
1289 #define RT5677_I2S_PD8_2 (0x1 << 0)
1301 #define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
1307 #define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
1313 #define RT5677_DSP_BUS_PD_2 (0x1 << 0)
1327 #define RT5677_PLL_K_BP (0x1 << 5)
1337 #define RT5677_PLL_M_BP (0x1 << 11)
1339 #define RT5677_PLL_UPDATE_PLL1 (0x1 << 1)
1346 #define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
1352 #define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
1358 #define RT5677_MCLK_SRC_MASK (0x1 << 10)
1361 #define RT5677_MCLK2_SRC (0x1 << 10)
1362 #define RT5677_PLL1_PD_MASK (0x1 << 8)
1365 #define RT5677_PLL1_PD_2 (0x1 << 8)
1369 #define RT5677_DAC_OSR_64 (0x1 << 6)
1374 #define RT5677_ADC_OSR_64 (0x1 << 4)
1378 #define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
1381 #define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
1385 #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1394 #define RT5677_DSP_ASRC_O_PLL1 (0x1 << 10)
1400 #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8)
1403 #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
1406 #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
1481 #define RT5677_VAD_OUT_SRC_RATE_MASK (0x1 << 11)
1483 #define RT5677_VAD_OUT_SRC_MASK (0x1 << 10)
1509 #define RT5677_SEL_SRC_OB23 (0x1 << 4)
1511 #define RT5677_SEL_SRC_OB01 (0x1 << 3)
1513 #define RT5677_SEL_SRC_IB45 (0x1 << 2)
1515 #define RT5677_SEL_SRC_IB23 (0x1 << 1)
1517 #define RT5677_SEL_SRC_IB01 (0x1 << 0)
1529 #define RT5677_STA_GPIO_JD1 (0x1 << 15)
1531 #define RT5677_EN_IRQ_GPIO_JD1 (0x1 << 14)
1533 #define RT5677_EN_GPIO_JD1_STICKY (0x1 << 13)
1535 #define RT5677_INV_GPIO_JD1 (0x1 << 12)
1537 #define RT5677_STA_GPIO_JD2 (0x1 << 11)
1539 #define RT5677_EN_IRQ_GPIO_JD2 (0x1 << 10)
1541 #define RT5677_EN_GPIO_JD2_STICKY (0x1 << 9)
1543 #define RT5677_INV_GPIO_JD2 (0x1 << 8)
1545 #define RT5677_STA_MICBIAS1_OVCD (0x1 << 7)
1547 #define RT5677_EN_IRQ_MICBIAS1_OVCD (0x1 << 6)
1549 #define RT5677_EN_MICBIAS1_OVCD_STICKY (0x1 << 5)
1551 #define RT5677_INV_MICBIAS1_OVCD (0x1 << 4)
1553 #define RT5677_STA_GPIO_JD3 (0x1 << 3)
1555 #define RT5677_EN_IRQ_GPIO_JD3 (0x1 << 2)
1557 #define RT5677_EN_GPIO_JD3_STICKY (0x1 << 1)
1559 #define RT5677_INV_GPIO_JD3 (0x1 << 0)
1563 #define RT5677_GPIO6_STATUS_MASK (0x1 << 5)
1565 #define RT5677_GPIO5_STATUS_MASK (0x1 << 4)
1567 #define RT5677_GPIO4_STATUS_MASK (0x1 << 3)
1569 #define RT5677_GPIO3_STATUS_MASK (0x1 << 2)
1571 #define RT5677_GPIO2_STATUS_MASK (0x1 << 1)
1573 #define RT5677_GPIO1_STATUS_MASK (0x1 << 0)
1577 #define RT5677_GPIO1_PIN_MASK (0x1 << 15)
1580 #define RT5677_GPIO1_PIN_IRQ (0x1 << 15)
1581 #define RT5677_IPTV_MODE_MASK (0x1 << 14)
1584 #define RT5677_IPTV_MODE_IPTV (0x1 << 14)
1585 #define RT5677_FUNC_MODE_MASK (0x1 << 13)
1588 #define RT5677_FUNC_MODE_JTAG (0x1 << 13)
1591 #define RT5677_GPIOx_DIR_MASK (0x1 << 2)
1594 #define RT5677_GPIOx_DIR_OUT (0x1 << 2)
1595 #define RT5677_GPIOx_OUT_MASK (0x1 << 1)
1598 #define RT5677_GPIOx_OUT_HI (0x1 << 1)
1599 #define RT5677_GPIOx_P_MASK (0x1 << 0)
1602 #define RT5677_GPIOx_P_INV (0x1 << 0)
1607 #define RT5677_IRQ_DEBOUNCE_SEL_RC (0x1 << 3)
1611 #define RT5677_DSP_IB_01_H (0x1 << 15)
1613 #define RT5677_DSP_IB_23_H (0x1 << 14)
1615 #define RT5677_DSP_IB_45_H (0x1 << 13)
1617 #define RT5677_DSP_IB_6_H (0x1 << 12)
1619 #define RT5677_DSP_IB_7_H (0x1 << 11)
1621 #define RT5677_DSP_IB_8_H (0x1 << 10)
1623 #define RT5677_DSP_IB_9_H (0x1 << 9)
1625 #define RT5677_DSP_IB_01_L (0x1 << 7)
1627 #define RT5677_DSP_IB_23_L (0x1 << 6)
1629 #define RT5677_DSP_IB_45_L (0x1 << 5)
1631 #define RT5677_DSP_IB_6_L (0x1 << 4)
1633 #define RT5677_DSP_IB_7_L (0x1 << 3)
1635 #define RT5677_DSP_IB_8_L (0x1 << 2)
1637 #define RT5677_DSP_IB_9_L (0x1 << 1)
1641 #define RT5677_GPIO5_FUNC_MASK (0x1 << 9)
1643 #define RT5677_GPIO5_FUNC_DMIC (0x1 << 9)
1717 RT5677_DA_STEREO_FILTER = 0x1,
1718 RT5677_DA_MONO2_L_FILTER = (0x1 << 1),
1719 RT5677_DA_MONO2_R_FILTER = (0x1 << 2),
1720 RT5677_DA_MONO3_L_FILTER = (0x1 << 3),
1721 RT5677_DA_MONO3_R_FILTER = (0x1 << 4),
1722 RT5677_DA_MONO4_L_FILTER = (0x1 << 5),
1723 RT5677_DA_MONO4_R_FILTER = (0x1 << 6),
1724 RT5677_AD_STEREO1_FILTER = (0x1 << 7),
1725 RT5677_AD_STEREO2_FILTER = (0x1 << 8),
1726 RT5677_AD_STEREO3_FILTER = (0x1 << 9),
1727 RT5677_AD_STEREO4_FILTER = (0x1 << 10),
1728 RT5677_AD_MONO_L_FILTER = (0x1 << 11),
1729 RT5677_AD_MONO_R_FILTER = (0x1 << 12),
1730 RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),
1731 RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),
1732 RT5677_I2S1_SOURCE = (0x1 << 15),
1733 RT5677_I2S2_SOURCE = (0x1 << 16),
1734 RT5677_I2S3_SOURCE = (0x1 << 17),
1735 RT5677_I2S4_SOURCE = (0x1 << 18),