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Searched refs:lane_mask (Results 1 - 25 of 44) sorted by relevance

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/kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/
H A Dcamss-csiphy-2ph-1-0.c32 u8 lane_mask; in csiphy_get_lane_mask() local
35 lane_mask = 1 << CAMSS_CSI_PHY_LN_CLK; in csiphy_get_lane_mask()
38 lane_mask |= 1 << lane_cfg->data[i].pos; in csiphy_get_lane_mask()
40 return lane_mask; in csiphy_get_lane_mask()
99 s64 link_freq, u8 lane_mask) in csiphy_lanes_enable()
114 val |= lane_mask << 1; in csiphy_lanes_enable()
97 csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, s64 link_freq, u8 lane_mask) csiphy_lanes_enable() argument
H A Dcamss-csiphy-3ph-1-0.c455 u8 lane_mask; in csiphy_get_lane_mask() local
458 lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; in csiphy_get_lane_mask()
461 lane_mask |= 1 << lane_cfg->data[i].pos; in csiphy_get_lane_mask()
463 return lane_mask; in csiphy_get_lane_mask()
468 s64 link_freq, u8 lane_mask) in csiphy_lanes_enable()
466 csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, s64 link_freq, u8 lane_mask) csiphy_lanes_enable() argument
H A Dcamss-csiphy.h60 s64 link_freq, u8 lane_mask);
H A Dcamss-csiphy.c246 u8 lane_mask = csiphy->ops->get_lane_mask(&cfg->csi2->lane_cfg); in csiphy_stream_on() local
262 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { in csiphy_stream_on()
275 csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); in csiphy_stream_on()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_combo_phy.c265 u8 lane_mask; in intel_combo_phy_power_up_lanes() local
272 lane_mask = PWR_DOWN_LN_3_1_0; in intel_combo_phy_power_up_lanes()
275 lane_mask = PWR_DOWN_LN_3_1; in intel_combo_phy_power_up_lanes()
278 lane_mask = PWR_DOWN_LN_3; in intel_combo_phy_power_up_lanes()
284 lane_mask = PWR_UP_ALL_LANES; in intel_combo_phy_power_up_lanes()
290 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : in intel_combo_phy_power_up_lanes()
294 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : in intel_combo_phy_power_up_lanes()
301 lane_mask = PWR_UP_ALL_LANES; in intel_combo_phy_power_up_lanes()
307 PWR_DOWN_LN_MASK, lane_mask); in intel_combo_phy_power_up_lanes()
H A Dintel_cx0_phy.c40 static int lane_mask_to_lane(u8 lane_mask) in lane_mask_to_lane() argument
42 if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) || in lane_mask_to_lane()
43 hweight8(lane_mask) != 1)) in lane_mask_to_lane()
46 return ilog2(lane_mask); in lane_mask_to_lane()
193 u8 lane_mask, u16 addr) in intel_cx0_read()
195 int lane = lane_mask_to_lane(lane_mask); in intel_cx0_read()
270 u8 lane_mask, u16 addr, u8 data, bool committed) in intel_cx0_write()
274 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_write()
320 u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) in intel_cx0_rmw()
324 for_each_cx0_lane_in_mask(lane_mask, lan in intel_cx0_rmw()
192 intel_cx0_read(struct drm_i915_private *i915, enum port port, u8 lane_mask, u16 addr) intel_cx0_read() argument
269 intel_cx0_write(struct drm_i915_private *i915, enum port port, u8 lane_mask, u16 addr, u8 data, bool committed) intel_cx0_write() argument
319 intel_cx0_rmw(struct drm_i915_private *i915, enum port port, u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) intel_cx0_rmw() argument
2442 intel_cx0_get_powerdown_update(u8 lane_mask) intel_cx0_get_powerdown_update() argument
2453 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state) intel_cx0_get_powerdown_state() argument
2464 intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915, enum port port, u8 lane_mask, u8 state) intel_cx0_powerdown_change_sequence() argument
2510 intel_cx0_get_pclk_refclk_request(u8 lane_mask) intel_cx0_get_pclk_refclk_request() argument
2521 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) intel_cx0_get_pclk_refclk_ack() argument
2539 u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : intel_cx0_phy_lane_reset() local
2675 intel_cx0_get_pclk_pll_request(u8 lane_mask) intel_cx0_get_pclk_pll_request() argument
2686 intel_cx0_get_pclk_pll_ack(u8 lane_mask) intel_cx0_get_pclk_pll_ack() argument
[all...]
H A Dintel_tc.c267 u32 lane_mask; in intel_tc_port_get_lane_mask() local
269 lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); in intel_tc_port_get_lane_mask()
271 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); in intel_tc_port_get_lane_mask()
274 lane_mask &= DP_LANE_ASSIGNMENT_MASK(tc->phy_fia_idx); in intel_tc_port_get_lane_mask()
275 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(tc->phy_fia_idx); in intel_tc_port_get_lane_mask()
320 u32 lane_mask; in intel_tc_port_fia_max_lane_count() local
330 lane_mask = 0; in intel_tc_port_fia_max_lane_count()
332 lane_mask = intel_tc_port_get_lane_mask(dig_port); in intel_tc_port_fia_max_lane_count()
334 switch (lane_mask) { in intel_tc_port_fia_max_lane_count()
336 MISSING_CASE(lane_mask); in intel_tc_port_fia_max_lane_count()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_combo_phy.c305 u8 lane_mask; in intel_combo_phy_power_up_lanes() local
313 lane_mask = PWR_DOWN_LN_3_1_0; in intel_combo_phy_power_up_lanes()
316 lane_mask = PWR_DOWN_LN_3_1; in intel_combo_phy_power_up_lanes()
319 lane_mask = PWR_DOWN_LN_3; in intel_combo_phy_power_up_lanes()
325 lane_mask = PWR_UP_ALL_LANES; in intel_combo_phy_power_up_lanes()
331 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : in intel_combo_phy_power_up_lanes()
335 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : in intel_combo_phy_power_up_lanes()
342 lane_mask = PWR_UP_ALL_LANES; in intel_combo_phy_power_up_lanes()
349 val |= lane_mask << PWR_DOWN_LN_SHIFT; in intel_combo_phy_power_up_lanes()
H A Dintel_tc.c86 u32 lane_mask; in intel_tc_port_get_lane_mask() local
88 lane_mask = intel_uncore_read(uncore, in intel_tc_port_get_lane_mask()
91 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); in intel_tc_port_get_lane_mask()
94 lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx); in intel_tc_port_get_lane_mask()
95 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); in intel_tc_port_get_lane_mask()
118 u32 lane_mask; in intel_tc_port_fia_max_lane_count() local
125 lane_mask = 0; in intel_tc_port_fia_max_lane_count()
127 lane_mask = intel_tc_port_get_lane_mask(dig_port); in intel_tc_port_fia_max_lane_count()
129 switch (lane_mask) { in intel_tc_port_fia_max_lane_count()
131 MISSING_CASE(lane_mask); in intel_tc_port_fia_max_lane_count()
[all...]
/kernel/linux/linux-5.10/include/linux/platform_data/
H A Domapdss.h26 int (*dsi_enable_pads)(int dsi_id, unsigned int lane_mask);
27 void (*dsi_disable_pads)(int dsi_id, unsigned int lane_mask);
/kernel/linux/linux-6.6/include/linux/platform_data/
H A Domapdss.h26 int (*dsi_enable_pads)(int dsi_id, unsigned int lane_mask);
27 void (*dsi_disable_pads)(int dsi_id, unsigned int lane_mask);
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
H A Dcore.c60 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask) in dss_dsi_enable_pads() argument
67 return board_data->dsi_enable_pads(dsi_id, lane_mask); in dss_dsi_enable_pads()
70 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask) in dss_dsi_disable_pads() argument
77 return board_data->dsi_disable_pads(dsi_id, lane_mask); in dss_dsi_disable_pads()
H A Ddss.h192 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
193 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
/kernel/linux/linux-6.6/drivers/video/fbdev/omap2/omapfb/dss/
H A Dcore.c60 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask) in dss_dsi_enable_pads() argument
67 return board_data->dsi_enable_pads(dsi_id, lane_mask); in dss_dsi_enable_pads()
70 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask) in dss_dsi_disable_pads() argument
77 return board_data->dsi_disable_pads(dsi_id, lane_mask); in dss_dsi_disable_pads()
H A Ddss.h192 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
193 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
/kernel/linux/linux-5.10/drivers/media/platform/qcom/camss/
H A Dcamss-csiphy.c220 u8 lane_mask; in csiphy_get_lane_mask() local
223 lane_mask = 1 << lane_cfg->clk.pos; in csiphy_get_lane_mask()
226 lane_mask |= 1 << lane_cfg->data[i].pos; in csiphy_get_lane_mask()
228 return lane_mask; in csiphy_get_lane_mask()
244 u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); in csiphy_stream_on() local
263 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { in csiphy_stream_on()
273 csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask); in csiphy_stream_on()
H A Dcamss-csiphy-2ph-1-0.c86 u32 pixel_clock, u8 bpp, u8 lane_mask) in csiphy_lanes_enable()
102 val |= lane_mask << 1; in csiphy_lanes_enable()
84 csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, u32 pixel_clock, u8 bpp, u8 lane_mask) csiphy_lanes_enable() argument
H A Dcamss-csiphy.h53 u32 pixel_clock, u8 bpp, u8 lane_mask);
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
H A Ddisplay.c119 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) in omap_dsi_enable_pads() argument
122 return omap4_dsi_mux_pads(dsi_id, lane_mask); in omap_dsi_enable_pads()
127 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) in omap_dsi_disable_pads() argument
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
H A Ddisplay.c111 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) in omap_dsi_enable_pads() argument
114 return omap4_dsi_mux_pads(dsi_id, lane_mask); in omap_dsi_enable_pads()
119 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) in omap_dsi_disable_pads() argument
/kernel/linux/linux-5.10/drivers/media/platform/ti-vpe/
H A Dcal-camerarx.c69 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK; in cal_camerarx_lane_config() local
75 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); in cal_camerarx_lane_config()
82 lane_mask <<= 4; in cal_camerarx_lane_config()
84 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); in cal_camerarx_lane_config()
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c49 u8 lane_mask; member
56 .lane_mask = 0xff, \
63 .lane_mask = l, \
313 u8 lane_mask) in qmp_pcie_msm8996_configure_lane()
322 if (!(t->lane_mask & lane_mask)) in qmp_pcie_msm8996_configure_lane()
310 qmp_pcie_msm8996_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, u8 lane_mask) qmp_pcie_msm8996_configure_lane() argument
H A Dphy-qcom-qmp-usb-legacy.c72 u8 lane_mask; member
79 .lane_mask = 0xff, \
86 .lane_mask = l, \
735 u8 lane_mask) in qmp_usb_legacy_configure_lane()
744 if (!(t->lane_mask & lane_mask)) in qmp_usb_legacy_configure_lane()
732 qmp_usb_legacy_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, u8 lane_mask) qmp_usb_legacy_configure_lane() argument
/kernel/linux/linux-6.6/drivers/soc/hisilicon/
H A Dkunpeng_hccs.h127 u8 lane_mask; /* indicate which lanes are used. */ member
/kernel/linux/linux-6.6/drivers/media/platform/ti/cal/
H A Dcal-camerarx.c83 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK; in cal_camerarx_lane_config() local
89 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); in cal_camerarx_lane_config()
96 lane_mask <<= 4; in cal_camerarx_lane_config()
98 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); in cal_camerarx_lane_config()

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