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Searched refs:hwpwm (Results 1 - 25 of 90) sorted by relevance

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/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-pca9685.c144 regmap_read(pca->regmap, LED_N_ON_H(pwm->hwpwm), &value); in pca9685_pwm_gpio_get()
157 regmap_write(pca->regmap, LED_N_OFF_L(pwm->hwpwm), 0); in pca9685_pwm_gpio_set()
158 regmap_write(pca->regmap, LED_N_OFF_H(pwm->hwpwm), 0); in pca9685_pwm_gpio_set()
161 regmap_write(pca->regmap, LED_N_ON_H(pwm->hwpwm), on); in pca9685_pwm_gpio_set()
287 if (pwm->hwpwm >= PCA9685_MAXCHAN) in pca9685_pwm_config()
290 reg = LED_N_OFF_H(pwm->hwpwm); in pca9685_pwm_config()
299 if (pwm->hwpwm >= PCA9685_MAXCHAN) in pca9685_pwm_config()
302 reg = LED_N_OFF_L(pwm->hwpwm); in pca9685_pwm_config()
306 if (pwm->hwpwm >= PCA9685_MAXCHAN) in pca9685_pwm_config()
309 reg = LED_N_OFF_H(pwm->hwpwm); in pca9685_pwm_config()
[all...]
H A Dpwm-vt8500.c108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
109 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
112 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); in vt8500_pwm_config()
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
115 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); in vt8500_pwm_config()
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
120 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); in vt8500_pwm_config()
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
[all...]
H A Dpwm-zx.c41 static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, in zx_pwm_readl() argument
44 return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); in zx_pwm_readl()
47 static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, in zx_pwm_writel() argument
50 writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset); in zx_pwm_writel()
53 static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm, in zx_pwm_set_mask() argument
58 data = zx_pwm_readl(zpc, hwpwm, offset); in zx_pwm_set_mask()
61 zx_pwm_writel(zpc, hwpwm, offset, data); in zx_pwm_set_mask()
73 value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); in zx_pwm_get_state()
88 tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD); in zx_pwm_get_state()
92 tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUT in zx_pwm_get_state()
[all...]
H A Dpwm-jz4740.c57 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm)) in jz4740_pwm_request()
60 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); in jz4740_pwm_request()
92 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), in jz4740_pwm_enable()
96 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); in jz4740_pwm_enable()
109 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); in jz4740_pwm_disable()
110 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); in jz4740_pwm_disable()
117 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), in jz4740_pwm_disable()
121 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); in jz4740_pwm_disable()
179 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0); in jz4740_pwm_apply()
182 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), dut in jz4740_pwm_apply()
[all...]
H A Dpwm-sun4i.c130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) ! in sun4i_pwm_apply()
[all...]
H A Dpwm-bcm-iproc.c90 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
95 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
108 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_get_state()
113 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
117 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
163 iproc_pwmc_disable(ip, pwm->hwpwm); in iproc_pwmc_apply()
167 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); in iproc_pwmc_apply()
168 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_apply()
172 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
173 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
[all...]
H A Dpwm-sprd.c73 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
85 pwm->hwpwm); in sprd_pwm_get_state()
89 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
103 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
108 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
122 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
152 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
153 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
154 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
164 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
[all...]
H A Dpwm-twl.c83 base = pwm->hwpwm * 3; in twl_pwm_config()
107 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
113 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
137 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
143 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_disable()
159 if (pwm->hwpwm == 1) { in twl4030_pwm_request()
197 if (pwm->hwpwm == 1) in twl4030_pwm_free()
229 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); in twl6030_pwm_enable()
230 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_enable()
252 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMX in twl6030_pwm_disable()
[all...]
H A Dpwm-atmel.c178 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
180 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
183 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
193 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
195 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
212 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
219 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
227 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
250 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_apply()
278 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CM in atmel_pwm_apply()
[all...]
H A Dpwm-stmpe.c48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
74 pwm->hwpwm); in stmpe_24xx_pwm_disable()
78 value = ret & ~BIT(pwm->hwpwm); in stmpe_24xx_pwm_disable()
83 pwm->hwpwm); in stmpe_24xx_pwm_disable()
117 pin = pwm->hwpwm; in stmpe_24xx_pwm_config()
128 pwm->hwpwm); in stmpe_24xx_pwm_config()
134 switch (pwm->hwpwm) { in stmpe_24xx_pwm_config()
153 pwm->hwpwm, duty_n in stmpe_24xx_pwm_config()
[all...]
H A Dpwm-bcm2835.c44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
57 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_free()
81 pc->base + DUTY(pwm->hwpwm)); in bcm2835_pwm_config()
82 writel(period, pc->base + PERIOD(pwm->hwpwm)); in bcm2835_pwm_config()
93 value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_enable()
105 value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_disable()
118 value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_set_polarity()
120 value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_set_polarity()
H A Dpwm-berlin.c115 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_config()
120 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_config()
122 berlin_pwm_writel(pwm, pwm_dev->hwpwm, duty, BERLIN_PWM_DUTY); in berlin_pwm_config()
123 berlin_pwm_writel(pwm, pwm_dev->hwpwm, period, BERLIN_PWM_TCNT); in berlin_pwm_config()
135 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
142 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
152 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN); in berlin_pwm_enable()
154 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_enable()
165 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN); in berlin_pwm_disable()
167 berlin_pwm_writel(pwm, pwm_dev->hwpwm, valu in berlin_pwm_disable()
[all...]
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-vt8500.c105 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
106 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
108 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
109 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); in vt8500_pwm_config()
111 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
112 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); in vt8500_pwm_config()
114 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
116 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
117 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); in vt8500_pwm_config()
135 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
[all...]
H A Dpwm-jz4740.c57 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm)) in jz4740_pwm_request()
60 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); in jz4740_pwm_request()
92 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_enable()
95 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); in jz4740_pwm_enable()
108 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); in jz4740_pwm_disable()
109 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); in jz4740_pwm_disable()
116 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_disable()
119 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); in jz4740_pwm_disable()
177 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0); in jz4740_pwm_apply()
180 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), dut in jz4740_pwm_apply()
[all...]
H A Dpwm-sunplus.c69 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
73 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
101 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); in sunplus_pwm_apply()
105 mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
107 mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
110 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
111 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
113 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
119 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
121 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
[all...]
H A Dpwm-sun4i.c130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
267 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
274 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
277 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) ! in sun4i_pwm_apply()
[all...]
H A Dpwm-atmel.c247 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
249 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
252 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
254 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); in atmel_pwm_update_cdty()
263 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
275 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_disable()
277 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
285 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CM in atmel_pwm_apply()
[all...]
H A Dpwm-bcm-iproc.c80 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
85 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
98 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_get_state()
103 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
107 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
155 iproc_pwmc_disable(ip, pwm->hwpwm); in iproc_pwmc_apply()
159 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); in iproc_pwmc_apply()
160 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_apply()
164 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
165 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
[all...]
H A Dpwm-microchip-core.c82 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()
83 shift = pwm->hwpwm & 7; in mchp_core_pwm_enable()
90 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); in mchp_core_pwm_enable()
91 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; in mchp_core_pwm_enable()
98 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) in mchp_core_pwm_enable()
181 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
182 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
311 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); in mchp_core_pwm_apply_locked()
368 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_apply()
387 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_get_state()
[all...]
H A Dpwm-sprd.c74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
86 pwm->hwpwm); in sprd_pwm_get_state()
90 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
104 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
109 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
125 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
155 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
[all...]
H A Dpwm-twl.c83 base = pwm->hwpwm * 3; in twl_pwm_config()
107 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
113 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
137 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
143 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_disable()
159 if (pwm->hwpwm == 1) { in twl4030_pwm_request()
197 if (pwm->hwpwm == 1) in twl4030_pwm_free()
229 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); in twl6030_pwm_enable()
230 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_enable()
252 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMX in twl6030_pwm_disable()
[all...]
H A Dpwm-stmpe.c48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
74 pwm->hwpwm); in stmpe_24xx_pwm_disable()
78 value = ret & ~BIT(pwm->hwpwm); in stmpe_24xx_pwm_disable()
83 pwm->hwpwm); in stmpe_24xx_pwm_disable()
118 pin = pwm->hwpwm; in stmpe_24xx_pwm_config()
129 pwm->hwpwm); in stmpe_24xx_pwm_config()
135 switch (pwm->hwpwm) { in stmpe_24xx_pwm_config()
154 pwm->hwpwm, duty_n in stmpe_24xx_pwm_config()
[all...]
H A Dpwm-bcm2835.c44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
57 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_free()
103 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm)); in bcm2835_pwm_apply()
107 writel(val, pc->base + DUTY(pwm->hwpwm)); in bcm2835_pwm_apply()
113 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_apply()
115 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_apply()
119 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_apply()
121 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_apply()
H A Dpwm-rz-mtu3.c134 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) in rz_mtu3_get_channel() argument
140 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) in rz_mtu3_get_channel()
148 u32 hwpwm) in rz_mtu3_pwm_is_ch_enabled()
154 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); in rz_mtu3_pwm_is_ch_enabled()
159 if (priv->map->base_pwm_number == hwpwm) in rz_mtu3_pwm_is_ch_enabled()
174 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_request()
203 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_free()
226 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_enable()
231 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_enable()
252 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_disable()
147 rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) rz_mtu3_pwm_is_ch_enabled() argument
[all...]
H A Dpwm-visconti.c53 writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
99 writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_apply()
100 writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_apply()
101 writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
112 period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_get_state()
113 duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_get_state()
114 pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_get_state()

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