Lines Matching refs:hwpwm
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
278 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
281 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
282 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
286 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
287 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
291 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
293 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
295 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
298 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
309 if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
310 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
320 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
321 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);