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/kernel/linux/linux-5.10/drivers/clk/socfpga/
H A Dclk-periph-a10.c28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-periph.c26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
61 u32 div_reg[3]; in __socfpga_periph_init() local
71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
74 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
75 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
77 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-gate-a10.c29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
98 u32 div_reg[3]; in __socfpga_gate_init() local
130 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
132 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
133 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
134 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
136 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
H A Dclk-gate.c98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
102 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
174 u32 div_reg[3]; in socfpga_gate_init() local
214 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
216 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
217 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
218 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
220 socfpga_clk->div_reg in socfpga_gate_init()
[all...]
H A Dclk-gate-s10.c22 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
23 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
36 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
87 if (clks->div_reg) in s10_register_gate()
88 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
90 socfpga_clk->div_reg = NULL; in s10_register_gate()
H A Dclk.h47 void __iomem *div_reg; member
50 u32 width; /* only valid if div_reg != 0 */
51 u32 shift; /* only valid if div_reg != 0 */
60 void __iomem *div_reg; member
62 u32 width; /* only valid if div_reg != 0 */
63 u32 shift; /* only valid if div_reg != 0 */
H A Dstratix10-clk.h55 unsigned long div_reg; member
/kernel/linux/linux-6.6/drivers/clk/socfpga/
H A Dclk-periph-a10.c28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-gate-a10.c29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
46 u32 div_reg[3]; in __socfpga_gate_init() local
77 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
79 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
80 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
81 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
83 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
H A Dclk-periph.c26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
61 u32 div_reg[3]; in __socfpga_periph_init() local
71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
74 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
75 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
77 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-gate.c96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()
100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_get_div()
140 u32 div_reg[3]; in socfpga_gate_init() local
176 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
178 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
179 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
180 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
182 socfpga_clk->div_reg in socfpga_gate_init()
[all...]
H A Dclk-gate-s10.c29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
150 socfpga_clk->div_reg = NULL; in s10_register_gate()
205 if (clks->div_reg) in agilex_register_gate()
206 socfpga_clk->div_reg = regbase + clks->div_reg; in agilex_register_gate()
[all...]
H A Dclk.h47 void __iomem *div_reg; member
50 u32 width; /* only valid if div_reg != 0 */
51 u32 shift; /* only valid if div_reg != 0 */
59 void __iomem *div_reg; member
61 u32 width; /* only valid if div_reg != 0 */
62 u32 shift; /* only valid if div_reg != 0 */
/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-bcm2835.c491 u32 div_reg; member
1009 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1095 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1917 .div_reg = CM_OTPDIV,
1929 .div_reg = CM_TIMERDIV,
1940 .div_reg = CM_TSENSDIV,
1947 .div_reg = CM_TECDIV,
1956 .div_reg = CM_H264DIV,
1964 .div_reg = CM_ISPDIV,
1977 .div_reg
[all...]
/kernel/linux/linux-6.6/drivers/clk/bcm/
H A Dclk-bcm2835.c492 u32 div_reg; member
1032 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1123 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1945 .div_reg = CM_OTPDIV,
1957 .div_reg = CM_TIMERDIV,
1968 .div_reg = CM_TSENSDIV,
1975 .div_reg = CM_TECDIV,
1984 .div_reg = CM_H264DIV,
1992 .div_reg = CM_ISPDIV,
2005 .div_reg
[all...]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c410 int div_reg; member
425 .div_reg = CLK_AUDDIV_2,
438 .div_reg = CLK_AUDDIV_2,
451 .div_reg = CLK_AUDDIV_2,
464 .div_reg = CLK_AUDDIV_2,
477 .div_reg = CLK_AUDDIV_3,
490 .div_reg = CLK_AUDDIV_2,
500 .div_reg = CLK_AUDDIV_3,
513 .div_reg = CLK_AUDDIV_3,
526 .div_reg
[all...]
/kernel/linux/linux-5.10/sound/soc/jz4740/
H A Djz4740-i2s.c285 uint32_t ctrl, div_reg; in jz4740_i2s_hw_params() local
290 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); in jz4740_i2s_hw_params()
312 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
313 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
319 div_reg &= ~I2SDIV_IDV_MASK; in jz4740_i2s_hw_params()
320 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; in jz4740_i2s_hw_params()
322 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
323 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
328 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); in jz4740_i2s_hw_params()
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-sn-f-ospi.c192 u32 div_reg; in f_ospi_config_clk() local
198 div_reg = OSPI_CLK_CTL_DIV_1; in f_ospi_config_clk()
201 div_reg = OSPI_CLK_CTL_DIV_1; in f_ospi_config_clk()
203 div_reg = OSPI_CLK_CTL_DIV_2; in f_ospi_config_clk()
205 div_reg = OSPI_CLK_CTL_DIV_4; in f_ospi_config_clk()
207 div_reg = OSPI_CLK_CTL_DIV_8; in f_ospi_config_clk()
211 div_reg = OSPI_CLK_CTL_DIV_8; in f_ospi_config_clk()
224 | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg); in f_ospi_config_clk()
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-vt8500.c22 void __iomem *div_reg; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
189 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
225 u32 en_reg, div_reg; in vtwm_device_clk_init() local
255 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
257 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-vt8500.c22 void __iomem *div_reg; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
189 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
225 u32 en_reg, div_reg; in vtwm_device_clk_init() local
255 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
257 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
H A Dclk-en7523.c38 u16 div_reg; member
106 .div_reg = REG_SPI_CLK_DIV_SEL,
179 reg = desc->div_reg ? desc->div_reg : desc->base_reg; in en7523_get_div()
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
H A Dclk-hi3620.c226 u32 div_reg; member
242 void __iomem *div_reg; member
372 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
374 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
432 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
H A Dclk-hi3620.c225 u32 div_reg; member
241 void __iomem *div_reg; member
371 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
373 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
431 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mtk.h183 u32 div_reg; member
194 .div_reg = _reg, \
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mtk.h189 u32 div_reg; member
200 .div_reg = _reg, \

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