Lines Matching refs:div_reg
96 else if (socfpgaclk->div_reg) {
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
140 u32 div_reg[3];
176 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
178 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
179 socfpga_clk->shift = div_reg[1];
180 socfpga_clk->width = div_reg[2];
182 socfpga_clk->div_reg = NULL;