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Searched refs:clocks (Results 1 - 25 of 231) sorted by relevance

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/kernel/linux/linux-5.10/tools/testing/selftests/timens/
H A Dtimens.c39 static struct test_clock clocks[] = { variable
96 if (check_skip(clocks[clock_index].id)) in test_gettime()
99 switch (clocks[clock_index].id) { in test_gettime()
109 if (_gettime(clocks[clock_index].id, &parent_ts_old, raw_syscall)) in test_gettime()
118 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
124 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
132 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
138 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
141 clock_settime(clocks[clock_index].id, &cur_ts); in test_gettime()
146 clocks[clock_inde in test_gettime()
[all...]
/kernel/linux/linux-6.6/tools/testing/selftests/timens/
H A Dtimens.c37 static struct test_clock clocks[] = { variable
94 if (check_skip(clocks[clock_index].id)) in test_gettime()
97 switch (clocks[clock_index].id) { in test_gettime()
107 if (_gettime(clocks[clock_index].id, &parent_ts_old, raw_syscall)) in test_gettime()
116 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
122 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
130 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
136 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
139 clock_settime(clocks[clock_index].id, &cur_ts); in test_gettime()
144 clocks[clock_inde in test_gettime()
[all...]
/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks
[all...]
H A Dclk-bcm21664.c25 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
67 .clocks = CLOCKS("ref_crystal",
79 .clocks = CLOCKS("ref_crystal",
91 .clocks = CLOCKS("ref_crystal",
103 .clocks = CLOCKS("ref_crystal",
114 .clocks = CLOCKS("ref_32k"), /* Verify */
119 .clocks = CLOCKS("ref_32k"), /* Verify */
124 .clocks = CLOCKS("ref_32k"), /* Verify */
129 .clocks
[all...]
/kernel/linux/linux-6.6/drivers/clk/bcm/
H A Dclk-bcm281xx.c19 .clocks = CLOCKS("ref_crystal"),
35 .clocks = CLOCKS("bbl_32k",
44 .clocks = CLOCKS("ref_crystal",
53 .clocks = CLOCKS("var_312m",
77 .clocks = CLOCKS("ref_crystal",
96 .clocks = CLOCKS("ref_crystal",
108 .clocks = CLOCKS("ref_crystal",
120 .clocks = CLOCKS("ref_crystal",
132 .clocks = CLOCKS("ref_crystal",
144 .clocks
[all...]
H A Dclk-bcm21664.c17 .clocks = CLOCKS("ref_crystal"),
35 .clocks = CLOCKS("bbl_32k",
59 .clocks = CLOCKS("ref_crystal",
71 .clocks = CLOCKS("ref_crystal",
83 .clocks = CLOCKS("ref_crystal",
95 .clocks = CLOCKS("ref_crystal",
106 .clocks = CLOCKS("ref_32k"), /* Verify */
111 .clocks = CLOCKS("ref_32k"), /* Verify */
116 .clocks = CLOCKS("ref_32k"), /* Verify */
121 .clocks
[all...]
/kernel/linux/linux-5.10/drivers/clk/renesas/
H A Dr9a06g032-clocks.c280 * These are not hardware clocks, but are needed to handle the special
320 clk_rdesc_set(struct r9a06g032_priv *clocks, in clk_rdesc_set() argument
323 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); in clk_rdesc_set()
331 clk_rdesc_get(struct r9a06g032_priv *clocks, in clk_rdesc_get() argument
334 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); in clk_rdesc_get()
347 struct r9a06g032_priv *clocks; member
389 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, in r9a06g032_attach_dev()
434 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, in r9a06g032_clk_gate_set() argument
441 spin_lock_irqsave(&clocks->lock, flags); in r9a06g032_clk_gate_set()
442 clk_rdesc_set(clocks, in r9a06g032_clk_gate_set()
500 r9a06g032_register_gate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) r9a06g032_register_gate() argument
543 struct r9a06g032_priv *clocks; global() member
670 r9a06g032_register_div(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) r9a06g032_register_div() argument
723 struct r9a06g032_priv *clocks; global() member
754 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) r9a06g032_register_bitsel() argument
792 struct r9a06g032_priv *clocks; global() member
844 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, uint16_t sel) r9a06g032_register_dualgate() argument
898 struct r9a06g032_priv *clocks; r9a06g032_clocks_probe() local
[all...]
/kernel/linux/linux-5.10/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_pm.c35 pm->clocks[i] = devm_clk_get(pm->device, pm->clk_names[i]); in s5p_mfc_init_pm()
36 if (IS_ERR(pm->clocks[i])) { in s5p_mfc_init_pm()
37 /* additional clocks are optional */ in s5p_mfc_init_pm()
38 if (i && PTR_ERR(pm->clocks[i]) == -ENOENT) { in s5p_mfc_init_pm()
39 pm->clocks[i] = NULL; in s5p_mfc_init_pm()
44 return PTR_ERR(pm->clocks[i]); in s5p_mfc_init_pm()
49 pm->clock_gate = pm->clocks[0]; in s5p_mfc_init_pm()
89 ret = clk_prepare_enable(pm->clocks[i]); in s5p_mfc_power_on()
104 clk_disable_unprepare(pm->clocks[i]); in s5p_mfc_power_on()
117 clk_disable_unprepare(pm->clocks[ in s5p_mfc_power_off()
[all...]
/kernel/linux/linux-6.6/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_pm.c35 pm->clocks[i] = devm_clk_get(pm->device, pm->clk_names[i]); in s5p_mfc_init_pm()
36 if (IS_ERR(pm->clocks[i])) { in s5p_mfc_init_pm()
37 /* additional clocks are optional */ in s5p_mfc_init_pm()
38 if (i && PTR_ERR(pm->clocks[i]) == -ENOENT) { in s5p_mfc_init_pm()
39 pm->clocks[i] = NULL; in s5p_mfc_init_pm()
44 return PTR_ERR(pm->clocks[i]); in s5p_mfc_init_pm()
49 pm->clock_gate = pm->clocks[0]; in s5p_mfc_init_pm()
87 ret = clk_prepare_enable(pm->clocks[i]); in s5p_mfc_power_on()
101 clk_disable_unprepare(pm->clocks[i]); in s5p_mfc_power_on()
114 clk_disable_unprepare(pm->clocks[ in s5p_mfc_power_off()
[all...]
/kernel/linux/linux-6.6/drivers/clk/renesas/
H A Dr9a06g032-clocks.c626 * These are not hardware clocks, but are needed to handle the special
696 static void clk_rdesc_set(struct r9a06g032_priv *clocks, in clk_rdesc_set() argument
699 u32 __iomem *reg = clocks->reg + (rb.reg * 4); in clk_rdesc_set()
710 static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb) in clk_rdesc_get() argument
712 u32 __iomem *reg = clocks->reg + (rb.reg * 4); in clk_rdesc_get()
725 struct r9a06g032_priv *clocks; member
767 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, in r9a06g032_attach_dev()
812 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, in r9a06g032_clk_gate_set() argument
819 spin_lock_irqsave(&clocks->lock, flags); in r9a06g032_clk_gate_set()
820 clk_rdesc_set(clocks, in r9a06g032_clk_gate_set()
874 r9a06g032_register_gate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) r9a06g032_register_gate() argument
917 struct r9a06g032_priv *clocks; global() member
1045 r9a06g032_register_div(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) r9a06g032_register_div() argument
1098 struct r9a06g032_priv *clocks; global() member
1130 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) r9a06g032_register_bitsel() argument
1168 struct r9a06g032_priv *clocks; global() member
1220 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, struct regbit sel) r9a06g032_register_dualgate() argument
1270 r9a06g032_init_h2mode(struct r9a06g032_priv *clocks) r9a06g032_init_h2mode() argument
1297 struct r9a06g032_priv *clocks; r9a06g032_clocks_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-bpmp.c424 struct tegra_bpmp_clk_info *clocks; in tegra_bpmp_probe_clocks() local
437 clocks = kcalloc(max_id + 1, sizeof(*clocks), GFP_KERNEL); in tegra_bpmp_probe_clocks()
438 if (!clocks) in tegra_bpmp_probe_clocks()
442 struct tegra_bpmp_clk_info *info = &clocks[count]; in tegra_bpmp_probe_clocks()
469 *clocksp = clocks; in tegra_bpmp_probe_clocks()
475 tegra_bpmp_clk_id_to_index(const struct tegra_bpmp_clk_info *clocks, in tegra_bpmp_clk_id_to_index() argument
481 if (clocks[i].id == id) in tegra_bpmp_clk_id_to_index()
488 tegra_bpmp_clk_find(const struct tegra_bpmp_clk_info *clocks, in tegra_bpmp_clk_find() argument
493 i = tegra_bpmp_clk_id_to_index(clocks, num_clock in tegra_bpmp_clk_find()
502 tegra_bpmp_clk_register(struct tegra_bpmp *bpmp, const struct tegra_bpmp_clk_info *info, const struct tegra_bpmp_clk_info *clocks, unsigned int num_clocks) tegra_bpmp_clk_register() argument
678 struct tegra_bpmp_clk_info *clocks; tegra_bpmp_init_clocks() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/ingenic/
H A Dtcu.c3 * JZ47xx SoCs TCU clocks driver
54 struct clk_hw_onecell_data *clocks; member
267 struct clk_hw_onecell_data *clocks) in ingenic_tcu_register_clock()
292 clocks->hws[idx] = &tcu_clk->hw; in ingenic_tcu_register_clock()
363 tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT), in ingenic_tcu_probe()
365 if (!tcu->clocks) { in ingenic_tcu_probe()
370 tcu->clocks->num = TCU_CLK_COUNT; in ingenic_tcu_probe()
375 tcu->clocks); in ingenic_tcu_probe()
383 * We set EXT as the default parent clock for all the TCU clocks in ingenic_tcu_probe()
264 ingenic_tcu_register_clock(struct ingenic_tcu *tcu, unsigned int idx, enum tcu_clk_parent parent, const struct ingenic_tcu_clk_info *info, struct clk_hw_onecell_data *clocks) ingenic_tcu_register_clock() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/ingenic/
H A Dtcu.c3 * JZ47xx SoCs TCU clocks driver
55 struct clk_hw_onecell_data *clocks; member
271 struct clk_hw_onecell_data *clocks) in ingenic_tcu_register_clock()
296 clocks->hws[idx] = &tcu_clk->hw; in ingenic_tcu_register_clock()
382 tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT), in ingenic_tcu_probe()
384 if (!tcu->clocks) { in ingenic_tcu_probe()
389 tcu->clocks->num = TCU_CLK_COUNT; in ingenic_tcu_probe()
394 tcu->clocks); in ingenic_tcu_probe()
402 * We set EXT as the default parent clock for all the TCU clocks in ingenic_tcu_probe()
268 ingenic_tcu_register_clock(struct ingenic_tcu *tcu, unsigned int idx, enum tcu_clk_parent parent, const struct ingenic_tcu_clk_info *info, struct clk_hw_onecell_data *clocks) ingenic_tcu_register_clock() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-bpmp.c401 struct tegra_bpmp_clk_info *clocks; in tegra_bpmp_probe_clocks() local
414 clocks = kcalloc(max_id + 1, sizeof(*clocks), GFP_KERNEL); in tegra_bpmp_probe_clocks()
415 if (!clocks) in tegra_bpmp_probe_clocks()
419 struct tegra_bpmp_clk_info *info = &clocks[count]; in tegra_bpmp_probe_clocks()
446 *clocksp = clocks; in tegra_bpmp_probe_clocks()
452 tegra_bpmp_clk_find(const struct tegra_bpmp_clk_info *clocks, in tegra_bpmp_clk_find() argument
458 if (clocks[i].id == id) in tegra_bpmp_clk_find()
459 return &clocks[i]; in tegra_bpmp_clk_find()
467 const struct tegra_bpmp_clk_info *clocks, in tegra_bpmp_clk_register()
465 tegra_bpmp_clk_register(struct tegra_bpmp *bpmp, const struct tegra_bpmp_clk_info *info, const struct tegra_bpmp_clk_info *clocks, unsigned int num_clocks) tegra_bpmp_clk_register() argument
601 struct tegra_bpmp_clk_info *clocks; tegra_bpmp_init_clocks() local
[all...]
/kernel/linux/linux-5.10/sound/soc/mediatek/mt8173/
H A Dmt8173-afe-pcm.c150 struct clk *clocks[MT8173_CLK_NUM]; member
330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], in mt8173_afe_i2s_prepare()
332 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], in mt8173_afe_i2s_prepare()
353 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], in mt8173_afe_hdmi_startup()
354 afe_priv->clocks[MT8173_CLK_I2S3_B]); in mt8173_afe_hdmi_startup()
367 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], in mt8173_afe_hdmi_shutdown()
368 afe_priv->clocks[MT8173_CLK_I2S3_B]); in mt8173_afe_hdmi_shutdown()
380 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], in mt8173_afe_hdmi_prepare()
382 afe_priv->clocks[MT8173_CLK_I2S3_B], in mt8173_afe_hdmi_prepare()
962 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_ in mt8173_afe_runtime_suspend()
[all...]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8173/
H A Dmt8173-afe-pcm.c150 struct clk *clocks[MT8173_CLK_NUM]; member
328 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], in mt8173_afe_i2s_prepare()
330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], in mt8173_afe_i2s_prepare()
351 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], in mt8173_afe_hdmi_startup()
352 afe_priv->clocks[MT8173_CLK_I2S3_B]); in mt8173_afe_hdmi_startup()
365 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], in mt8173_afe_hdmi_shutdown()
366 afe_priv->clocks[MT8173_CLK_I2S3_B]); in mt8173_afe_hdmi_shutdown()
378 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], in mt8173_afe_hdmi_prepare()
380 afe_priv->clocks[MT8173_CLK_I2S3_B], in mt8173_afe_hdmi_prepare()
960 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_ in mt8173_afe_runtime_suspend()
[all...]
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dtlv320aic32x4.c703 struct clk_bulk_data clocks[] = { in aic32x4_setup_clocks() local
711 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); in aic32x4_setup_clocks()
757 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) in aic32x4_setup_clocks()
760 clk_set_rate(clocks[0].clk, in aic32x4_setup_clocks()
763 clk_set_rate(clocks[1].clk, in aic32x4_setup_clocks()
766 clk_set_rate(clocks[2].clk, in aic32x4_setup_clocks()
771 clk_set_rate(clocks[3].clk, in aic32x4_setup_clocks()
774 clk_set_rate(clocks[4].clk, in aic32x4_setup_clocks()
779 clk_set_rate(clocks[ in aic32x4_setup_clocks()
858 struct clk_bulk_data clocks[] = { aic32x4_set_bias_level() local
883 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); aic32x4_set_bias_level() local
974 struct clk_bulk_data clocks[] = { aic32x4_component_probe() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
H A Drcar_lvds.c73 struct clk *dotclkin[2]; /* External DU clocks */
74 } clocks; member
332 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll, in __rcar_lvds_pll_setup_d3_e3()
334 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll, in __rcar_lvds_pll_setup_d3_e3()
336 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, in __rcar_lvds_pll_setup_d3_e3()
381 ret = clk_prepare_enable(lvds->clocks.mod); in rcar_lvds_clk_enable()
402 clk_disable_unprepare(lvds->clocks.mod); in rcar_lvds_clk_disable()
461 ret = clk_prepare_enable(lvds->clocks.mod); in __rcar_lvds_atomic_enable()
626 clk_disable_unprepare(lvds->clocks.mod); in rcar_lvds_atomic_disable()
851 lvds->clocks in rcar_lvds_get_clocks()
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dingenic-sysost.c3 * Ingenic XBurst SoCs SYSOST clocks driver
82 struct clk_hw_onecell_data *clocks; member
271 struct clk_hw_onecell_data *clocks) in ingenic_ost_register_clock()
296 clocks->hws[idx] = &ost_clk->hw; in ingenic_ost_register_clock()
455 ost->clocks = kzalloc(struct_size(ost->clocks, hws, ost->soc_info->num_channels), in ingenic_ost_probe()
457 if (!ost->clocks) { in ingenic_ost_probe()
462 ost->clocks->num = ost->soc_info->num_channels; in ingenic_ost_probe()
464 for (i = 0; i < ost->clocks->num; i++) { in ingenic_ost_probe()
465 ret = ingenic_ost_register_clock(ost, i, &ingenic_ost_clk_info[i], ost->clocks); in ingenic_ost_probe()
269 ingenic_ost_register_clock(struct ingenic_ost *ost, unsigned int idx, const struct ingenic_ost_clk_info *info, struct clk_hw_onecell_data *clocks) ingenic_ost_register_clock() argument
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dingenic-sysost.c3 * Ingenic XBurst SoCs SYSOST clocks driver
81 struct clk_hw_onecell_data *clocks; member
272 struct clk_hw_onecell_data *clocks) in ingenic_ost_register_clock()
297 clocks->hws[idx] = &ost_clk->hw; in ingenic_ost_register_clock()
456 ost->clocks = kzalloc(struct_size(ost->clocks, hws, ost->soc_info->num_channels), in ingenic_ost_probe()
458 if (!ost->clocks) { in ingenic_ost_probe()
463 ost->clocks->num = ost->soc_info->num_channels; in ingenic_ost_probe()
465 for (i = 0; i < ost->clocks->num; i++) { in ingenic_ost_probe()
466 ret = ingenic_ost_register_clock(ost, i, &x1000_ost_clk_info[i], ost->clocks); in ingenic_ost_probe()
270 ingenic_ost_register_clock(struct ingenic_ost *ost, unsigned int idx, const struct ingenic_ost_clk_info *info, struct clk_hw_onecell_data *clocks) ingenic_ost_register_clock() argument
[all...]
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dtlv320aic32x4.c721 static struct clk_bulk_data clocks[] = { in aic32x4_setup_clocks() local
729 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); in aic32x4_setup_clocks()
788 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) in aic32x4_setup_clocks()
791 clk_set_rate(clocks[0].clk, in aic32x4_setup_clocks()
794 clk_set_rate(clocks[1].clk, in aic32x4_setup_clocks()
797 clk_set_rate(clocks[2].clk, in aic32x4_setup_clocks()
802 clk_set_rate(clocks[3].clk, in aic32x4_setup_clocks()
805 clk_set_rate(clocks[4].clk, in aic32x4_setup_clocks()
810 clk_set_rate(clocks[ in aic32x4_setup_clocks()
889 static struct clk_bulk_data clocks[] = { aic32x4_set_bias_level() local
914 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); aic32x4_set_bias_level() local
1005 static struct clk_bulk_data clocks[] = { aic32x4_component_probe() local
1154 static struct clk_bulk_data clocks[] = { aic32x4_tas2505_component_probe() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/ti/
H A Dadpll.c177 struct ti_adpll_clock *clocks; member
214 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
215 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
227 d->clocks[index].cl = cl; in ti_adpll_setup_clock()
649 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_s()
658 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
668 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
676 d->clocks[TI_ADPLL_DIV2].clk, in ti_adpll_init_children_adpll_s()
677 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
683 "clkout2", d->clocks[TI_ADPLL_M in ti_adpll_init_children_adpll_s()
[all...]
/kernel/linux/linux-6.6/drivers/clk/ti/
H A Dadpll.c168 struct ti_adpll_clock *clocks; member
205 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
206 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
218 d->clocks[index].cl = cl; in ti_adpll_setup_clock()
640 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_s()
649 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
659 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
667 d->clocks[TI_ADPLL_DIV2].clk, in ti_adpll_init_children_adpll_s()
668 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
674 "clkout2", d->clocks[TI_ADPLL_M in ti_adpll_init_children_adpll_s()
[all...]
/kernel/linux/linux-5.10/arch/mips/ar7/
H A Dclock.c240 struct tnetd7300_clocks *clocks = in tnetd7300_init_clocks() local
245 &clocks->bus, bootcr, AR7_AFE_CLOCK); in tnetd7300_init_clocks()
249 &clocks->cpu, bootcr, AR7_AFE_CLOCK); in tnetd7300_init_clocks()
254 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, in tnetd7300_init_clocks()
257 iounmap(clocks); in tnetd7300_init_clocks()
324 struct tnetd7200_clocks *clocks = in tnetd7200_init_clocks() local
342 tnetd7200_set_clock(dsp_base, &clocks->dsp, in tnetd7200_init_clocks()
351 tnetd7200_set_clock(cpu_base, &clocks->cpu, in tnetd7200_init_clocks()
364 tnetd7200_set_clock(cpu_base, &clocks->cpu, in tnetd7200_init_clocks()
372 tnetd7200_set_clock(dsp_base, &clocks in tnetd7200_init_clocks()
[all...]
/kernel/linux/linux-5.10/drivers/ata/
H A Dpata_atp867x.c142 unsigned char clocks = clk; in atp867x_get_active_clocks_shifted() local
149 clocks++; in atp867x_get_active_clocks_shifted()
151 switch (clocks) { in atp867x_get_active_clocks_shifted()
153 clocks = 1; in atp867x_get_active_clocks_shifted()
162 clocks = 7; /* 12 clk */ in atp867x_get_active_clocks_shifted()
166 clocks = 0; in atp867x_get_active_clocks_shifted()
171 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; in atp867x_get_active_clocks_shifted()
176 unsigned char clocks = clk; in atp867x_get_recover_clocks_shifted() local
178 switch (clocks) { in atp867x_get_recover_clocks_shifted()
180 clocks in atp867x_get_recover_clocks_shifted()
[all...]

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