Lines Matching refs:clocks
150 struct clk *clocks[MT8173_CLK_NUM];
330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
332 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
353 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
354 afe_priv->clocks[MT8173_CLK_I2S3_B]);
367 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
368 afe_priv->clocks[MT8173_CLK_I2S3_B]);
380 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
382 afe_priv->clocks[MT8173_CLK_I2S3_B],
962 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
963 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
964 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
965 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
966 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
967 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
968 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
978 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
982 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
986 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
990 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
994 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
997 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1000 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1019 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1021 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1023 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1025 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1027 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1029 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1039 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1040 if (IS_ERR(afe_priv->clocks[i])) {
1043 return PTR_ERR(afe_priv->clocks[i]);
1046 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
1047 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */