Lines Matching refs:clocks
626 * These are not hardware clocks, but are needed to handle the special
696 static void clk_rdesc_set(struct r9a06g032_priv *clocks,
699 u32 __iomem *reg = clocks->reg + (rb.reg * 4);
710 static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb)
712 u32 __iomem *reg = clocks->reg + (rb.reg * 4);
725 struct r9a06g032_priv *clocks;
767 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,
812 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
819 spin_lock_irqsave(&clocks->lock, flags);
820 clk_rdesc_set(clocks, g->gate, on);
822 clk_rdesc_set(clocks, g->reset, 1);
823 spin_unlock_irqrestore(&clocks->lock, flags);
832 spin_lock_irqsave(&clocks->lock, flags);
833 clk_rdesc_set(clocks, g->ready, on);
835 clk_rdesc_set(clocks, g->midle, !on);
836 spin_unlock_irqrestore(&clocks->lock, flags);
845 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
853 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
861 if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
864 return clk_rdesc_get(g->clocks, g->gate.gate);
874 r9a06g032_register_gate(struct r9a06g032_priv *clocks,
892 g->clocks = clocks;
898 * important here, some clocks are already in use by the CM3, we
917 struct r9a06g032_priv *clocks;
933 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
998 * The serial driver *shouldn't* play with these clocks anyway, there's
1021 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
1045 r9a06g032_register_div(struct r9a06g032_priv *clocks,
1064 div->clocks = clocks;
1087 * each of the clock source - the used clock source (for all sub clocks)
1089 * That single bit affects all sub-clocks, and therefore needs to change the
1098 struct r9a06g032_priv *clocks;
1110 return clk_rdesc_get(set->clocks, set->selector);
1117 /* a single bit in the register selects one of two parent clocks */
1118 clk_rdesc_set(set->clocks, set->selector, !!index);
1130 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
1153 g->clocks = clocks;
1168 struct r9a06g032_priv *clocks;
1180 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
1183 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
1184 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
1208 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
1210 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
1220 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
1233 g->clocks = clocks;
1248 * important here, some clocks are already in use by the CM3, we
1270 static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
1281 usb = readl(clocks->reg + R9A06G032_SYSCTRL_USB);
1290 writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB);
1297 struct r9a06g032_priv *clocks;
1304 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
1307 if (!clocks || !clks)
1310 spin_lock_init(&clocks->lock);
1312 clocks->data.clks = clks;
1313 clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
1319 clocks->reg = of_iomap(np, 0);
1320 if (WARN_ON(!clocks->reg))
1323 r9a06g032_init_h2mode(clocks);
1328 __clk_get_name(clocks->data.clks[d->source - 1]) :
1339 clk = r9a06g032_register_gate(clocks, parent_name, d);
1342 clk = r9a06g032_register_div(clocks, parent_name, d);
1347 clk = r9a06g032_register_bitsel(clocks, parent_name, d);
1350 clk = r9a06g032_register_dualgate(clocks, parent_name,
1355 clocks->data.clks[d->index] = clk;
1357 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
1370 sysctrl_priv = clocks;